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2010”N“x IEEEŠÖ¼Žx•”Šw¶Œ¤‹†§—ãÜ

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Marie Engelene J. Obieni”ŽŽmŒãŠú‰Û’ö3”Nj
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Marie Engelene J. Obien, Satoshi Ohtake, and Hideo Fujiwara, "Constrained ATPG for Functional RTL Circuits Using F-Scan," 2010 IEEE International Test Conference, Paper 21.1, Nov. 2010.
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•½¬ 23 ”N 2 ŒŽ

IEEE WRTLT 2008 Best Paper Award

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Chia Yee Ooi(uŽt, ƒ}ƒŒ[ƒVƒAH‰È‘åŠw)
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Hideo Fujiwara, Chia Yee Ooi, and Yuki Shimizu, "Enhancement of Test Environment Generation for Assignment Decision Diagrams"
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•½¬ 21 ”N 11 ŒŽ
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IEEE ASICON 2009 Excellent Student Paper Award

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Marie Engelene J. Obien(”ŽŽmŒãŠú‰Û’ö‚Q”N)
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Marie Engelene J. Obien and Hideo Fujiwara, "F-Scan: An Approach to Functional RTL Scan for Assignment Decision Diagrams", Proc. IEEE 8th International Conference on ASIC (ASICON2009), pp. 589- 592, Oct. 2009.
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•½¬ 21 ”N 10 ŒŽ
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IEEE Computer Society Outstanding Contribution Award

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“¡Œ´ G—Y ‹³Žö
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•½¬ 21 ”N 5 ŒŽ
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IEEE WRTLT 2007 Best Paper Award

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‹gì —SŽ÷ •‹³(‘²‹Æ¶FŒ»L“‡Žs—§‘åŠw)
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Yuki Yoshikawa, Satoshi Ohtake and Hideo Fujiwara, "RTL Don't Care Path Identification and Synthesis for Transforming Don't Care Paths into False Paths"
ŽóÜ”NŒŽF
•½¬ 20 ”N 11 ŒŽ

2007”N“x IEEEŠÖ¼Žx•”Šw¶Œ¤‹†§—ãÜ

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Fawnizu Azmadi HUSSINi”ŽŽmŒãŠú‰Û’ö3”Nj
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Fawnizu Azmadi Hussin, Tomokazu Yoneda, and Hideo Fujiwara, "Optimization of NoC Wrapper Design under Bandwidth and Test Time Constraints," Proceeding of the IEEE European Test Symposium 2007, pp. 35-40, May, 2007.
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•½¬ 20 ”N 2 ŒŽ

2006”N“x IPSJ Digital Courier‘DˆäŽáŽè§—ãÜ

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‹gì—SŽ÷i”ŽŽmŒãŠú‰Û’ö2”Nj
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Yuki Yoshikawa, Satoshi Ohtake, Michiko Inoue, and Hideo Fujiwara, "Non-scan Design for Single-Port-Change Delay Fault Testability," Information Processing Society of Japan, Vol. 47, No. 6, pp. 1619-1628, June 2006.
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•½¬ 19 ”N 3 ŒŽ

2006”N“x IEEEŠÖ¼Žx•”Šw¶Œ¤‹†§—ãÜ

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‹gì—SŽ÷i”ŽŽmŒãŠú‰Û’ö2”Nj
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Yuki Yoshikawa, Satoshi Ohtake, Michiko Inoue, and Hideo Fujiwara, "Design for Testability Based on Single-Port-Change Delay Testing for Data Paths," Proceedings of IEEE the 14th Asian Test Symposium 2005 (ATS'05), pp. 254-259, Dec. 2005.
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•½¬ 19 ”N 2 ŒŽ

IEEE WRTLT 2005 Best Paper Award

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’†—¢ ¹l i”ŽŽmŒãŠú‰Û’ö‚Q”Nj
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Kewal K. Saluja ‹³Žö iƒEƒBƒXƒRƒ“ƒVƒ“‘åŠwj
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Masato Nakazato, Satoshi Ohtake, Kewal K. Saluja and Hideo Fujiwara "Acceleration of Test Generation for Sequential Circuits Using Knowledge Obtained from Synthesis for Testability," Proc. of IEEE 6th Workshop on RTL and High Level Testing (WRTLT'05), pp.50-60, June 2005.
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•½¬ 18 ”N 11 ŒŽ

2005”N“x IEEEŠÖ¼Žx•”Šw¶Œ¤‹†§—ãÜ

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’†—¢¹li”ŽŽmŒãŠú‰Û’ö‚P”Nj
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Masato Nakazato, Satoshi Ohtake, Kewal K. Saluja and Hideo Fujiwara "Acceleration of Test Generation for Sequential Circuits Using Knowledge Obtained from Synthesis for Testability," Proc. of IEEE 6th Workshop on RTL and High Level Testing (WRTLT'05), pp.50-60, June 2005.
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•½¬ 18 ”N 2 ŒŽ

IEEE DELTA 2006 Best Paper Award

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Michel Renovell ‹³Žöiƒ‚ƒ“ƒyƒŠƒG‘æ“ñ‘åŠw LIRMMŒ¤‹†ŠCƒtƒ‰ƒ“ƒXj
Mariane Comte ”ŽŽmiNAIST-COE ƒ|ƒXƒgƒhƒNŒ¤‹†ˆõGŒ»ÝAƒ‚ƒ“ƒyƒŠƒG‘æ“ñ‘åŠw LIRMMŒ¤‹†Š•‹³ŽöCƒtƒ‰ƒ“ƒXj
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Michel Renovell, Mariane Comte, Satoshi Ohtake and Hideo Fujiwara, "Electrical Behavior of GOS Fault affected Domino Logic Cell," Third IEEE International Workshop on Electronic Design, Test & Applications (DELTA 2006),17-19 Jan. 2006
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•½¬ 18 ”N 1 ŒŽ

IEEE Computer Society Meritorious Service Award

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•½¬ 17 ”N 11 ŒŽ

IEEE Computer Society Continuing Service Award

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•½¬ 17 ”N 11 ŒŽ

IEEE ŠÖ¼Žx•”Šw¶Œ¤‹†§—ãÜ

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ŠâŠ_ „i–{Œ¤‹†‰È”ñí‹ÎŒ¤‹†ˆõC•½¬ 16 ”N 9 ŒŽ–{Œ¤‹†‰È”ŽŽmŒãŠú‰Û’öC—¹j
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Tsuyoshi Iwagaki, Satoshi Ohtake and Hideo Fujiwara, "A design methodology to realize delay testable controllers using state transition information," Proc. 9th IEEE European Test Symposium (ETS '04), pp. 168-173, May 2004.
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•½¬ 17 ”N 2 ŒŽ

IEEE ATS'02 Best Paper Award

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Erik Larsson ”ŽŽmi“ú–{ŠwpU‹»‰ïŠO‘l“Á•ÊŒ¤‹†ŽÒGŒ»ÝALinkoeping Univ. •‹³ŽöAƒXƒG[ƒfƒ“j
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Erik Larsson, Klas Arvidsson, Hideo Fujiwara and Zebo Peng, "Integrated Test Scheduling, Test Parallelization and TAM Design," Proc. of IEEE the 11th Asian Test Symposium (ATS'02), pp. 397-404, Nov. 2002.
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•½¬ 16 ”N 11 ŒŽ

IEEE WRTLT '03 Best Paper Award

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ŠâŠ_ „i–{Œ¤‹†‰È”ñí‹ÎŒ¤‹†ˆõC•½¬ 16 ”N 9 ŒŽ–{Œ¤‹†‰È”ŽŽmŒãŠú‰Û’öC—¹j
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Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara, "An approach to non-scan design for delay fault testability of controllers," Digest of Papers IEEE the 4th Workshop on RTL and High Level Testing (WRTLT '03), pp. 79-85, Nov. 2003.
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•½¬ 16 ”N 11 ŒŽ

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•½¬ 16 ”N 3 ŒŽ

•½¬ 13 ”N“x“dŽqî•ñ’ʐMŠw‰ïî•ñƒVƒXƒeƒ€ƒ\ƒTƒCƒGƒeƒB˜_•¶Ü

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Kewal K. Saluja iƒEƒBƒXƒRƒ“ƒVƒ“‘åŠw‹³Žöj
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‚è ’q–çiƒVƒƒ[ƒvŠ”Ž®‰ïŽÐF•½¬ 12 ”N 3 ŒŽ–{Œ¤‹†‰È”ŽŽmŒãŠú‰Û’öC—¹j
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‰iˆä T‘¾˜Yi¼‰º“dŠíŽY‹ÆŠ”Ž®‰ïŽÐF•½¬ 15 ”N 3 ŒŽ–{Œ¤‹†‰È”ŽŽmŒãŠú‰Û’öC—¹j
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•½¬ 14 ”N 9 ŒŽ

IEEE Computer Society Outstanding Contribution Award

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•½¬ 13 ”N 11 ŒŽ

IEEE ATS '01 ŽR“c‹P•F‹L”OÜ

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Md. Altaf-Ul-Amini”ŽŽmŒãŠú‰Û’ö 1 ”Nj
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•½¬ 13 ”N 11 ŒŽ

IEEE Computer Society Certificate of Appreciation Award

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•½¬ 13 ”N 11 ŒŽ

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•½¬ 13 ”N 9 ŒŽ

î•ñ‰ÈŠwŒ¤‹†‰ÈÅ—DGŠw¶Ü

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•½¬ 12 ”N 3 ŒŽ

IEEE Computer Society Certificate of Appreciation Award

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•½¬12”N10ŒŽ

1999”N•À—ñˆ—ƒVƒ“ƒ|ƒWƒEƒ€ JSPP '99 Å—DG˜_•¶Ü

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•½¬ 11 ”N 6 ŒŽ

IEEE Computer Society Golden Core Member Award

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•½¬ 9 ”N 12 ŒŽ

•½¬ 8 ”N“x“dŽqî•ñ’ʐMŠw‰ïŠwp§—ãÜ

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•½¬ 9 ”N 3 ŒŽ

IEEE Computer Society Meritorious Service Award

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•½¬ 8 ”N 11 ŒŽ

‘åìo”ŏÜ

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•½¬ 6 ”N 11 ŒŽ

IEEE Computer Society Certificate of Appreciation Award

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•½¬ 3 ”N 10 ŒŽ

IEEE Fellow Award

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“dŽq’ʐMŠw‰ï Šwp§—ãÜ

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