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学術論文
[1]安留 誠吾, 増澤 利光, 辻野 嘉宏, 都倉 信樹,
"障害物の重みを考慮した最短経路問題 ,"
電子情報通信学会論文誌(DI), Vol. J76-D-I, No. 4, pp.157-163, Apr. 1993.
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[2]藤野 貴之, 藤原 秀雄,
"探索状態被覆性に基づく探索空間削減の一手法 ,"
電子情報通信学会論文誌(DI), Vol. J76-D-I, No. 5, pp.218-227, May 1993.
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[3]井上 美智子, 萩原 兼一, 都倉 信樹,
"完全ネットワークでの最小重み生成木構成分散問題のビット複雑度について ,"
電子情報通信学会論文誌(DI), Vol. J76-D-I, No. 7, pp.329-338, July 1993.
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[4]井上 美智子, 萩原 兼一, 都倉 信樹,
"超立方体状ネットワークでの最小重み生成木構成分散問題のメッセージ複雑度について ,"
電子情報通信学会論文誌(DI), Vol. J76-D-I, No. 7, pp.405-406, July 1993.
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[5]Hideo Fujiwara and A. Yamamoto,
"Parity-scan design to reduce the cost of test application,"
IEEE Trans. on Computer-Aided Design, Vol. 12, No. 10, pp.1604-1611, Oct. 1993.
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[6]安留 誠吾, 増澤 利光, 辻野 嘉宏, 都倉 信樹,
"障害物のある平面上で水平線分に制限をおいた水平垂直線分からなる最短経路について ,"
電子情報通信学会論文誌(DI), Vol. J76-D-I, No. 10, pp.495-503, Oct. 1993.
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[7]増澤 利光, 片山 喜章,
"自己安定アルゴリズムについて ,"
情報処理, Vol. 34, No. 11, pp.1358-1365, Nov. 1993.
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[8]井上 智生, 米澤 友紀, 藤原 秀雄,
"テスト生成における並列処理の最適なシステム構成について ,"
電子情報通信学会論文誌(DI), Vol. J76-D-I, No. 11, pp.604-612, Nov. 1993.
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[9]Takayuki Fujino and Hideo Fujiwara,
"A search space pruning method for test pattern generation using search state dominance,"
J. of Circuits, Systems and Computers, Vol. 3, No. 4, pp.859-875, Dec. 1993.
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[10]三浦 康史, 増澤 利光, 都倉 信樹,
"距離に応じた計算量で最短経路木を求める分散アルゴリズム ,"
電子情報通信学会論文誌(DI), Vol. J77-D-I, No. 1, pp.21-32, Jan. 1994.
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[11]三浦 康史, 増澤 利光, 都倉 信樹,
"最短経路木更新問題を解く分散アルゴリズム ,"
電子情報通信学会論文誌(DI), Vol. J77-D-I, No. 1, pp.33-40, Jan. 1994.
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[12]藤原 秀雄,
"VLSI のテスト,"
電子情報通信学会学会誌, Vol. 77, No. 3, pp.288-295, Mar. 1994.
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[13]Tomoo Inoue, Tomonori Yonezawa and Hideo Fujiwara,
"Optimal granularity of parallel test generation on the client-agent-server model,"
Trans. of IPSJ, Vol. 35, No. 8, pp.1614-1623, Aug. 1994.
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[14]Wei Chen, K. Nakano, Toshimitsu Masuzawa and Nobuki Tokura,
"A parallel method for the prefix convex hulls problem,"
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E77-A, No. 10, pp.1675-1683, Oct. 1994.
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[15]宮下 健輔, 増澤 利光, 都倉 信樹,
"再構成アレー上の接頭部和問題について ,"
電子情報通信学会論文誌(DI), Vol. J77-D-I, No. 10, pp.703-711, Oct. 1994.
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[16]片山 喜章, 増澤 利光, 都倉 信樹,
"C デーモンによるリングの方向付け自己安定アルゴリズム,"
電子情報通信学会論文誌(DI), Vol. J77-D-I, No. 12, pp.777-784, Dec. 1994.
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[17]Akihiro Fujiwara, Toshimitsu Masuzawa and Hideo Fujiwara,
"An optimal parallel algorithm for the Euclidean distance map of 2-D binary images,"
Information Processing Letters, Vol. 54, No. 5, 1995.
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[18]Hideo Fujiwara and Tomoo Inoue,
"Optimal granularity and scheme of parallel test generation in a distributed system,"
IEEE Trans. on Parallel and Distributed Systems, Vol. 6, No. 7, pp.677-686, July 1995.
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[19]藤原 暁宏, 増澤 利光, 藤原 秀雄,
"濃淡画像の連結成分を求める並列アルゴリズム ,"
電子情報通信学会論文誌(DI), Vol. J79-D-I, No. 5, pp.215-225, May 1996.
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[20]吉田 大輔, 増澤 利光, 藤原 秀雄,
"自律ロボット群のための停止故障耐性のある分散型問題解法 ,"
電子情報通信学会論文誌(DI), Vol. J79-D-I, No. 6, pp.320-330, June 1996.
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[21]Tomoo Inoue, Hironori Maeda and Hideo Fujiwara,
"On the effect of scheduling in test generation,"
IEICE Trans. on Information and Systems, Vol. E79-D, No. 8, pp.1190-1197, Aug. 1996.
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[22]Akihiro Fujiwara, Michiko Inoue, Toshimitsu Masuzawa and Hideo Fujiwara,
"A simple parallel algorithm for the medial axis transform,"
IEICE Trans.on Information and Systems (Special issue on Architecture, Algorithm and Networks for Massively Parallel Computing), Vol. E79-D, No. 8, pp.1038-1045, Aug. 1996.
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[23]Tomoo Inoue, Takaharu Fujii and Hideo Fujiwara,
"Performance analysis of parallel test generation for combinational circuits,"
IEICE Trans. on Information and Systems, Vol. E79-D, No. 9, pp.1257-1265, Sep. 1996.
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[24]道西 博行, 横平 徳美, 岡本 卓爾, 井上 智生, 藤原 秀雄,
"テーブル参照型 FPGA における論理ブロックの検査,"
電子情報通信学会(DI), Vol. J79-D-I, No. 12, pp.1141-1150, Dec. 1996.
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[25]高畠 勝之, 井上 美智子, 増澤 利光, 藤原 秀雄,
"スルー演算を用いた非スキャン方式によるデータパスのテスト容易化設計 ,"
電子情報通信学会論文誌(DI), Vol. J79-D-I, No. 12, pp.1063-1071, Dec. 1996.
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[26]四浦 洋, 井上 智生, 増澤 利光, 藤原 秀雄,
"部分スキャンによる同期化可能な有限状態機械の合成について ,"
電子情報通信学会論文誌(DI), Vol. J79-D-I, No. 12, pp.1046-1054, Dec. 1996.
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[27]藤原 秀雄, 大竹 哲史, 高崎 智也,
"組合せテスト生成複雑度でテスト生成可能な順序回路構造とその応用 ,"
電子情報通信学会論文誌(DI), Vol. J80-D-I, No. 2, pp.155-163, Feb. 1997.
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[28]Toshimitsu Masuzawa and Nobuki Tokura,
"An algorithm for finding the causal distributed breakpoint,"
Journal of Parallel and Distributed Computing, Vol. 42, No. 1, pp.60-66, Apr. 1997.
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[29]大竹 哲史, 井上 智生, 藤原 秀雄,
"回路疑似変換による順序回路テスト生成の一手法 ,"
情報処理学会論文誌, Vol. 38, No. 5, pp.1040-1049, May 1997.
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[30]Tomoo Inoue, Satoshi Miyazaki and Hideo Fujiwara,
"Universal fault diagnosis for lookup table FPGAs,"
IEEE Design & Test of Computers, Vol. 15, No. 1, Jan.-Mar., pp.39-44, 1998.
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[31]Michiko Inoue and Hideo Fujiwara,
"An approach to test synthesis from higher level,"
INTEGRATION the VLSI journal , Vol. 26, pp.101-116, 1998.
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[32]Michiko Inoue, Toshimitsu Masuzawa and Nobuki Tokura,
"Efficient linearizable implementation of shared FIFO queues and general objects on a distributed system,"
IEICE Trans.on Fundamentals (Special Section on Discrete Mathematics and Its Applications), Vol. E81-A, No. 5, pp.768-775, Mar. 1998.
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[33]高崎 智也, 井上 智生, 藤原 秀雄,
"内部平衡構造に基づく部分スキャン設計法の考察 ,"
電子情報通信学会論文誌(DI), Vol. J81-D-I, No. 3, pp.318-327, Mar. 1998.
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[34]Michiko Inoue, Kenji Noda, Takeshi Higashimura, Toshimitsu Masuzawa and Hideo Fujiwara,
"High-level synthesis for weakly testable data paths,"
IEICE Trans. on Information and Systems (Special Section on Test and Diagnosis of VLSI), Vol. E81-D, No. 7, pp.645-653, July 1998.
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[35]大竹 哲史, 増澤 利光, 藤原 秀雄,
"完全故障検出効率を保証するコントローラの非スキャンテスト容易化設計法 ,"
電子情報通信学会論文誌(DI), Vol. J81-D-I, No. 12, pp.1259-1270, Dec. 1998.
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[36]Akihiro Fujiwara, Michiko Inoue, Toshimitsu Masuzawa and Hideo Fujiwara,
"A cost optimal parallel algorithm for weighted distance transforms,"
Parallel computing, Vol. 25, No. 4, pp.405-416, 1999.
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[37]東村 剛嗣, 井上 美智子, 藤原 秀雄,
"弱可検査性のための設計目標抽出を利用したデータパス高位合成 ,"
電子情報通信学会論文誌(DI), Vol. J82-D-I, No. 2, pp.401-409, Feb. 1999.
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[38]大堀 力, 井上 美智子, 増澤 利光, 藤原 秀雄,
"分散移動システムのための前後関係保存放送プロトコル ,"
電子情報通信学会論文誌(DI), Vol. J82-D-I, No. 2, pp.425-435, Feb. 1999.
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[39]石水 隆, 藤原 暁宏, 井上 美智子, 増澤 利光, 藤原 秀雄,
"選択問題を解く BSP モデルおよび BSP* モデル上の並列アルゴリズム,"
電子情報通信学会論文誌 (DI), Vol. J82-D-I, No. 4, pp.533-542, Apr. 1999.
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[40]Hiroyuki Nichinishi, Tokumi Yokohira, Takuji Okamoto, Tomoo Inoue and Hideo Fujiwara,
"Testing for the programming circuit of SRAM-based FPGAs,"
IEICE Trans. on Information and Systems, Vol. E82-D, No. 6, pp.1051-1057, June 1999.
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[41]林 邦彦, 井上 美智子, 増澤 利光, 藤原 秀雄,
"直交順序を保存する方形の非交差配置問題 ,"
電子情報通信学会論文誌(DI), Vol. J82-D-I, No. 6, pp.679-690, June 1999.
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[42]細川 利典, 井上 智生, 平岡 敏洋, 藤原 秀雄,
"時間展開モデルを用いた無閉路順序回路のテスト系列圧縮方法 ,"
電子情報通信学会論文誌(DI), Vol. J82-D-I, No. 7, pp.869-878, July 1999.
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[43]和田 弘樹, 増澤 利光, Kewal K. Saluja, 藤原 秀雄,
"完全故障検出効率を保証するデータパスの非スキャンテスト容易化設計法 ,"
電子情報通信学会論文誌(DI), Vol. J82-D-I, No. 7, pp.843-851, July 1999.
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[44]Akihiro Fujiwara, Michiko Inoue and Toshimitsu Masuzawa,
"Parallel selection algorithms for CGM and BSP models with application to sorting,"
IPSJ Journal, Vol. 41, No. 5, pp.1500-1508, 2000.
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[45]守屋 宣, 井上 美智子, 増澤 利光, 藤原 秀雄,
"共有メモリマルチプロセッサシステムにおける同期時間最適な無待機時計合わせプロトコル ,"
電子情報通信学会論文誌文誌(DI), Vol. J83-D-I, No. 1, pp.99-109, Jan. 2000.
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[46]藤原 暁宏, 陳 慰, 増澤 利光, 都倉 信樹,
"2 分木の平衡分解木を求めるコスト最適な並列アルゴリズム,"
電子情報科学研究科通信学会論文誌(D-I), Vol. J83-D-I, No. 1, pp.90-98, Jan. 2000.
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[47]Takashi Ishimizu, Akihiro Fujiwara, Michiko Inoue, Toshimitsu Masuzawa and Hideo Fujiwara,
"Parallel algorithms for the all nearest neighbors of binary image on the BSP model,"
IEICE Transactions (D), Vol. E83-D, No. 2, pp.151-158, Feb. 2000.
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[48]高崎 智也, 井上 智生, 藤原 秀雄,
"無閉路部分スキャン設計に基づくデータパスのテスト容易化高位合成におけるバインディング手法 ,"
電子情報通信学会論文誌(DI) , Vol. J83-D-I, No. 2, pp.282-292, Feb. 2000.
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[49]Sen Moriya, Katsuro Suda, Michiko Inoue, Toshimitsu Masuzawa and Hideo Fujiwara,
"Wait-free linearizable distributed shared memory,"
IEICE Transactions on Information and Systems, Vol. E83-D, No. 8, pp.1611-1621, Aug. 2000.
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[50]Hideo Fujiwara,
"A new class of sequential circuits with combinational test generation complexity,"
IEEE Trans. on Comput., Vol. 49, No. 9, pp.895-905, Sep. 2000.
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[51]佐野 ちいほ, 三原 隆宏, 井上 智生, Debesh K. Das, 藤原 秀雄,
"ホールド機能を考慮した順序回路の部分スキャン設計法 ,"
電子情報通信学会, Vol. J83, No. 9, pp.981-990, Sep. 2000.
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[52]Satoshi Ohtake, Toshimitsu Masuzawa and Hideo Fujiwara,
"A non-scan approach to DFT for controllers achieving 100% fault efficiency,"
Journal of Electronic Testing: Theory and Applications (JETTA), Vol. 16, No. 5, pp.553-566, Oct. 2000.
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[53]X. Li, P.Y.S. Cheung and Hideo Fujiwara,
"LFSR-based deterministic TPG for two-pattern testing,"
Journal of Electronic Testing: Theory and Applications(JETTA), Vol. 16, No. 5, pp.419-426, Oct. 2000.
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[54]Hiroyoshi Matsui, Michiko Inoue, Toshimitsu Masuzawa and Hideo Fujiwara,
"Fault-tolerant and self-stabilizing protocols using an unreliable failure detector,"
IEICE Transactions on Information and Systems, Vol. E83-D, No. 10, pp.1831-1840, Oct. 2000.
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[55]井筒 稔, 和田 弘樹, 増澤 利光, 藤原 秀雄,
"レジスタ転送レベルデータパスの単一制御可検査性に基づく組込み自己テスト容易化設計法 ,"
電子情報通信学会論文誌(DI), Vol. J84-D-I, No. 1, pp.69-77, Jan. 2001.
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[56]浮穴 学慈, 長谷川 学, 片山 喜章, 増澤 利光, 藤原 秀雄,
"木ネットワーク上のヒープ順序構成自己安定プロトコル ,"
電子情報通信学会論文誌(DI), Vol. J84-D-I, No. 1, pp.48-57, Jan. 2001.
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[57]谷口 博人, 井上 美智子, 増澤 利光, 藤原 秀雄,
"アドホックネットワークにおけるクラスタ構成法 ,"
電子情報通信学会論文誌 (D1), Vol. J84-D-I, No. 2, pp.127-135, Feb. 2001.
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[58]和田 弘樹, 増澤 利光, 藤原 秀雄,
"演算器の強可検査性を保証するテスト容易化高位合成 ,"
電子情報通信学会論文誌 (D1), Vol. J84-D-I, No. 5, pp.466-473, May 2001.
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[59]永井 慎太郎, 和田 弘樹, 大竹 哲史, 藤原 秀雄,
"固定制御可検査性に基づく RTL 回路の非スキャンテスト容易化設計法,"
電子情報通信学会論文誌(DI), Vol. J84-D-I, No. 5, pp.454-465, May 2001.
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Abstract
[60]Yoshiaki Katayama, Eiichiou Ueda, Hideo Fujiwara and Toshimitsu Masuzawa,
"A latency optimal superstabilizing mutual exclusion protocol in unidirectional rings,"
Journal of Parallel and Distributed Computing, Vol. 62, pp.865-884, 2002.
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[61]Michiko Inoue, Emil Gizdarski and Hideo Fujiwara,
"Sequential circuits with combinational test generation complexity under single-fault assumption,"
Journal of Electronic Testing Theory and Applications, Vol. 18, No. 1, pp.55-62, Feb. 2002.
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[62]米田 友和, 藤原 秀雄,
"連続可検査性に基づくコアベースシステムオンチップのテスト容易化設計法 ,"
電子情報通信学会論文誌(DI), Vol. J85-D-I, No. 2, pp.173-183, Feb. 2002.
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[63]永井 慎太郎, 大竹 哲史, 藤原 秀雄,
"レジスタ転送レベルでのデータフロー依存型回路の階層テスト容易化設計法 ,"
情報処理学会論文誌 システムLSIの設計技術と設計自動化 特集号, Vol. 43, No. 5, pp.1278-1289, May 2002.
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[64]Md. Altaf-Ul-Amin, Satoshi Ohtake and Hideo Fujiwara,
"Design for hierarchical two-pattern testability of data paths,"
IEICE Trans. on Information and Systems, Vol. E85-D, No. 6, pp.975-984, June 2002.
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[65]山口 賢一, 和田 弘樹, 増澤 利光, 藤原 秀雄,
"レジスタ転送レベルデータパスの単一制御並行可検査性に基づく組込み自己テスト法 ,"
電子情報通信学会論文誌(DI), Vol. J85-D-I, No. 6, pp.527-537, June 2002.
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[66]Tomokazu Yoneda and Hideo Fujiwara,
"Design for consecutive testability of system-on-a-chip with built-in self testable cores,"
Journal of Electronic Testing: Theory and Applications (JETTA) Special Issue on Plug-and-Play Test Automation for System-on-a-Chip, Vol. 18, No. 4/5, pp.487-501, Aug. 2002.
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[67]Dong Xiang and Hideo Fujiwara,
"Handling the pin overhead problem of DFTs for high quality and at-speed test,"
IEEE Trans. on Computer Aided Design for Integrated Circuits and Systems, Vol. 21, No. 9, pp.1105-1113, Sep. 2002.
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[68]浮穴 学慈, 片山 喜章, 増澤 利光, 藤原 秀雄,
"非停止永久故障に耐性を有する自己安定生成木構成プロトコル ,"
電子情報通信学会論文誌 (DI), Vol. J85-D-I, No. 11, pp.1007-1014, Nov. 2002.
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[69]Emil Gizdarski and Hideo Fujiwara,
"SPIRIT: a highly robust combinational test generation algorithm,"
IEEE Trans. on Computer Aided Design for Integrated Circuits and Systems, Vol. 21, No. 12, pp.1446-1458, Dec. 2002.
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[70]Satoshi Ohtake, Hiroki Wada, Toshimitsu Masuzawa and Hideo Fujiwara,
"A non-scan DFT method at register-transfer level to achieve 100% fault efficiency,"
Trans. of IPSJ, Vol. 44, No. 5, pp.1266-1275, May 2003.
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[71]Md. Altaf-Ul-Amin, Satoshi Ohtake and Hideo Fujiwara,
"Design for two-pattern testability of controller-data path circuits,"
IEICE Trans. on Information and Systems, Vol. E86-D, No. 6, pp.1042-1049, June 2003.
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[72]山口 賢一, 井上 美智子, 藤原 秀雄,
"階層 BIST:低いハードウェアオーバヘッドを実現する test-per-clcok 方式 BIST,"
電子情報通信学会論文誌(DI), Vol. J86-D-1, No. 7, pp.469-479, July 2003.
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[73]Dong Xiang, Yi Xu and Hideo Fujiwara,
"Non-scan design for testability for synchronous sequential circuits based on conflict resolution,"
IEEE Trans. on Computers, Vol. 52, No. 8, pp.1063-1075, Aug. 2003.
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[74]神野 元彰, 井上 美智子, 藤原 秀雄,
"ホールドとスイッチの機能を考慮した内部平衡構造 ,"
電子情報通信学会論文誌(DI), Vol. J86-D-1, No. 9, pp.682-690, Sep. 2003.
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[75]Dong Xiang, Shan Gu and Hideo Fujiwara,
"Non-scan design for testability for synchronous sequential circuits based on fault-oriented conflict analysis ,"
IEICE Transactions on Information and Systems, Vol. E86-D, No. 11, pp.2407-2417, Nov. 2003.
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[76]三輪 俊二郎, 大竹 哲史, 藤原 秀雄,
"組合せテスト生成複雑度でパス遅延故障テスト生成可能な順序回路のクラス ,"
電子情報通信学会論文誌(DI), Vol. J86-D-I, No. 11, pp.809-820, Nov. 2003.
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[77]Toshinori Hosokawa, Hiroshi Date, Masahide Miyazaki, Michiaki Muraoka and Hideo Fujiwara,
"A test plan grouping method to shorten test length for RTL data paths under a test controller area constraint,"
IEICE Trans. on Information and Systems, Vol. E86-D, No. 12, pp.2674-2683, Dec. 2003.
BibTeX
IEICE
[78]岩垣 剛, 大竹 哲史, 藤原 秀雄,
"不連続再収斂順序回路の遅延故障に対するテスト生成法 ,"
電子情報通信学会論文誌 (DI), Vol. J86-D-I, No. 12, pp.872-883, Dec. 2003.
BibTeX
IEICE
[79]Masahide Miyazaki, Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka and Hideo Fujiwara,
"A DFT selection method fo reducing test application time of system-on-chips,"
IEICE Transactions on Information and Systems, Vol. E87-D, No. 3, pp.609-619, Mar. 2004.
BibTeX
IEICE
[80]Erik Larsson and Hideo Fujiwara,
"Preemptive system-on-chip test scheduling,"
IEICE Transactions on Information and Systems, Vol. E87-D, No. 3, pp.620-629, Mar. 2004.
BibTeX
IEICE
[81]Erik Larsson , Klas Arvidsson, Hideo Fujiwara and Zebo Peng,
"Efficient test solutions for core-based designs,"
IEEE Trans. on CAD, Vol. 23, No. 5, pp.758-775, May 2004.
BibTeX
[82]Debesh K. Das, Satoshi Ohtake and Hideo Fujiwara,
"New non-scan DFT techniques to achieve 100% fault efficiency,"
Journal of Electronic Testing, Vol. 20, No. 3, pp.315-323, June 2004.
BibTeX
[83]Tsuyoshi Iwagaki, Satoshi Ohtake and Hideo Fujiwara,
"A design scheme for delay testing of controllers using state transition information,"
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences (Special Section on VLSI Design and CAD Algorithms), Vol. E87-A, No. 12, pp.3200-3207, Dec. 2004.
BibTeX
IEICE
[84]米田 友和, 藤原 秀雄,
"レジスタ転送レベル回路に対する連続透明化設計法 ,"
電子情報通信学会論文誌(DI), Vol. J87-D-I, No. 12, pp.1110-1118, Dec. 2004.
BibTeX
IEICE
[85]Virendra Singh, Michiko Inoue, Kewal K. Saluja and Hideo Fujiwara,
"Delay fault testing of processor cores in functional mode,"
IEICE Trans. on Information and Systems, Vol. E88-D, No. 3, pp.610-618, Mar. 2005.
BibTeX
IEICE
[86]Dong Xiang, Ming-Jing Chen, Jia-guang Sun and Hideo Fujiwara,
"Improving test effectiveness of scan-based BIST by scan chain partitioning,"
IEEE Trans. on CAD, Vol. 24, No. 6, pp.916-927, June 2005.
BibTeX
[87]Yoshiyuki Nakamura, Jacob Savir and Hideo Fujiwara,
"Defect level vs. yield and fault coverage in the presence of an unreliable BIST,"
IEICE Trans. on Information and Systems, Vol. E88-D, No. 6, pp.1210-1216, June 2005.
BibTeX
IEICE
[88]大谷 浩平, 大竹 哲史, 藤原 秀雄,
"縮退故障のテスト生成アルゴリズムを用いたパス遅延故障に対するテスト生成法 ,"
電子情報通信学会和文論文誌(DI), Vol. J88-D-I, No. 6, pp.1057-1064, June 2005.
BibTeX
IEICE
[89]井上 美智子, 神戸 和子, Virendra Singh, 藤原 秀雄,
"縮退故障とパス遅延故障のためのプロセッサの命令レベル自己テスト法 ,"
電子情報通信学会和文論(DI), Vol. J88-D-I, No. 6, pp.1003-1011, June 2005.
BibTeX
IEICE
[90]Zhiqiang You, Ken-ichi Yamaguchi, Jacob Savir, Michiko Inoue and Hideo Fujiwara,
"Power-constrained test synthesis and scheduling algorithms for non-scan BIST-able RTL data paths,"
IEICE Transactions on Information and Systems, Vol. E88-D, No. 8, pp.1940-1947, Aug. 2005.
BibTeX
IEICE
[91]Chia Yee Ooi, Thomas Clouqueur and Hideo Fujiwara,
"Classification of sequential circuits based on tau^k notation and its applications,"
IEICE Transactions on Information and Systems, Vol. E88-D, No. 12, pp.2738-2747, Dec. 2005.
BibTeX
IEICE
[92]Erik Larsson and Hideo Fujiwara,
"System-on chip test scheduling with reconfigurable core wrappers,"
IEEE Trans. on Very Large Scale Integration (VLSI) Systems, pp.305-309, Mar. 2006.
BibTeX
[93]Yoshiyuki Nakamura, Thomas Clouqueur, Kewal K. Saluja and Hideo Fujiwara,
"Error identification in at-speed scan BIST environment in the presence of circuit and tester speed mismatch ,"
IEICE Trans. on Information and Systems, Vol. E89-D, No. 3, pp.1165-1172, Mar. 2006.
BibTeX
IEICE
[94]Masahide Miyazaki, Tomokazu Yoneda and Hideo Fujiwara,
"A memory grouping method for reducing memory BIST logic of system-on-chips,"
IEICE Transactions on Information and Systems, Vol. E89-D, No. 4, pp.1490-1497, Apr. 2006.
BibTeX
IEICE
[95]Yuki Yoshikawa, Satoshi Ohtake, Michiko Inoue and Hideo Fujiwara,
"Non-scan design for single-port-change delay fault testability,"
IPSJ Journal, Vol. 47, No. 6, pp.1619-1628, June 2006.
BibTeX
[96]Zhiqiang You, Tsuyoshi Iwagaki, Michiko Inoue and Hideo Fujiwara,
"A low power deterministic test using scan chain disable technique,"
IEICE Transactions on Information and Systems, Vol. E89-D, No. 6, pp.1931-1939, June 2006.
BibTeX
IEICE
[97]岩田 浩幸, 米田 友和, 大竹 哲史, 藤原 秀雄,
"完全故障検出効率を保証するRTLデータパスの部分強可検査性に基づくテスト容易化設計法 ,"
電子情報通信学会和文論文誌D-I(ディペンダブルコンピューティング特集号), Vol. 89-D, No. 8, pp.1643-1653, Aug. 2006.
BibTeX
IEICE
[98]Yoshiyuki Nakamura, Jacob Savir and Hideo Fujiwara,
"Effect of BIST pretest on IC defect level,"
IEICE Transactions on Information and Systems, Vol. E89-D, No. 10, pp.2626-2636, Oct. 2006.
BibTeX
IEICE
[99]Virendra Singh, Michiko Inoue, Kewal K. Saluja and Hideo Fujiwara,
"Instruction-based self-testing of delay faults in pipelined processors,"
IEEE Trans. on Very Large Scale Integration (VLSI)Systems, Vol. 14, No. 11, pp.1203-1215, Nov. 2006.
BibTeX
[100]Masato Nakazato, Satoshi Ohtake, Kewal K. Saluja and Hideo Fujiwara,
"Acceleration of test generation for sequential circuits using knowledge obtained from synthesis for testability,"
The IEICE Transactions on Information and Systems, Vol. E90-D, No. 1, pp.296-305, Jan. 2007.
BibTeX
[101]Dong Xiang, Kai-wei Li, Jia-guang Sun and Hideo Fujiwara,
"Reconfigured scan forest for test application cost, test data volume and test power reduction,"
IEEE Trans. on Computers, Vol. 56, No. 4, pp.557-562, Apr. 2007.
BibTeX
[102]Dong Xiang, Kai-wei Li, Hideo Fujiwara, Krishnaiyan Thulasiraman and Jia-guang Sun,
"Constraining transition propagation for low-power scan testing using a two-stage scan architecture,"
IEEE Trans. on Circuits and Systems, Vol. 54, No. 5, pp.450-454, May 2007.
BibTeX
[103]Yoshiyuki Nakamura, Thomas Clouqueur, Kewal K. Saluja and Hideo Fujiwara,
"Diagnosing at-speed scan BIST circuits using a low speed and low memory tester,"
IEEE Trans. on Very Large Scale Integration (VLSI) Systems, Vol. 15, No. 7, pp.790-800, July 2007.
BibTeX
[104]Chia Yee Ooi, Thomas Clouqueur and Hideo Fujiwara,
"Analysis of test generation complexity for stuck-at and path delay faults based on τ ^k-notation,"
IEICE Transactions on Information and Systems, Vol. E90-D, No. 8, pp.1202-1212, Aug. 2007.
BibTeX
IEICE
[105]Ilia Polian and Hideo Fujiwara,
"Functional constraints vs. test compression in scan-based delay testing,"
Theory and Applications (JETTA), Vol. 23, No. 5, pp.445-455, Oct. 2007.
BibTeX
[106]Dong Xiang, Ming-Jing Chen and Hideo Fujiwara,
"Using weighted scan enable signals to improve test effectiveness of scan-based BIST,"
IEEE Trans. on Computers, Vol. 56, No. 12, pp.1619-1628, Dec. 2007.
BibTeX
[107]Tsuyoshi Iwagaki, Satoshi Ohtake and Hideo Fujiwara,
"Broadside transition test generation for partial scan circuits through stuck-at test generation,"
IFIP International Federation for Information Processing, pp.301-306, 2008.
BibTeX
[108]Masato Nakazato, Michiko Inoue, Satoshi Ohtake and Hideo Fujiwara,
"Design for testability method to avoid error masking of software-based self-test for processors,"
IEICE Trans. on Information and Systems, Vol. E91-D, No. 3, pp.763-770, Mar. 2008.
BibTeX
IEICE
[109]Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orailoglu and Hideo Fujiwara,
"Scheduling power-constrained tests through the soc functional bus,"
IEICE Transactions on Information and Systems, Vol. E91-D, No. 3, pp.736-746, Mar. 2008.
BibTeX
IEICE
[110]Thomas Edison Yu, Tomokazu Yoneda, Danella Zhao and Hideo Fujiwara,
"Effective domain partitioning for multi-clock domain IP core wrapper design under power constraints,"
IEICE Transactions on Information and Systems, Vol. E91-D, No. 3, pp.807-814, Mar. 2008.
BibTeX
IEICE
[111]Tomokazu Yoneda, Kimihiko Masuda and Hideo Fujiwara,
"Test scheduling for multi-clock domain socs under power constraint,"
IEICE Transactions on Information and Systems, Vol. E91-D, No. 3, pp.747-755, Mar. 2008.
BibTeX
IEICE
[112]Dong Xiang, Yang Zhao, Krishnendu Chakrabarty and Hideo Fujiwara,
"A reconfigurable scan architecture with weighted scan-enable signals for deterministic BIST,"
IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 27, No. 6, pp.999-1012, June 2008.
BibTeX
[113]Fawnizu Azmadi Hussin, Tomokazu Yoneda and Hideo Fujiwara,
"NoC-compatible wrapper design and optimization under channel bandwidth and test time constraints,"
IEICE Transactions on Information and Systems, Vol. E91-D, No. 7, pp.2008-2017, July 2008.
BibTeX
IEICE
[114]Fawnizu Azmadi Hussin, Tomokazu Yoneda and Hideo Fujiwara,
"On noc bandwidth sharing for the optimization of area cost and test application time,"
IEICE Transactions on Information and Systems, Vol. E91-D, No. 7, pp.1999-2007, July 2008.
BibTeX
IEICE
[115]Hideo Fujiwara, Hiroyuki Iwata, Tomokazu Yoneda and Chia Yee Ooi,
"A non-scan design-for-testability for register-transfer level circuits to guarantee linear-depth time expansion models,"
IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 27, No. 9, pp.1535-1544, Sep. 2008.
BibTeX
[116]Thomas Edison Yu, Tomokazu Yoneda, Krishnendu Chakrabarty and Hideo Fujiwara,
"Thermal-aware test access mechanism and wrapper design optimization for system-on-chips,"
IEICE Transactions on Information and Systems, Vol. E91-D, No. 10, pp.2440-2448, Oct. 2008.
BibTeX
IEICE
[117]岡 伸也, Chia Yee Ooi, 市原 英行, 井上 智生, 藤原 秀雄,
"部分スルー可検査性に基づく順序回路のテスト生成法 ,"
電子情報通信学会論文誌(DI), Vol. Vol.J92-D, No. No.12, pp.2207-2216, Dec. 2009.
BibTeX
IEICE
[118]Ryoichi Inoue, Toshinori Hosokawa and Hideo Fujiwara,
"A fault dependent test generation method for state-observable FSMs to increase defect coverage under the test length constraint,"
IEICE Transactions on Information and Systems (Special Section on Test, Diagnosis and Verification of SOCs), Vol. 1. E93-D, No. 1, pp.24-32, Jan. 2010.
BibTeX
IEICE
[119]Hongxia Fang, Krishnendu Chakrabarty and Hideo Fujiwara,
"RTL DFT techniques to enhance defect coverage for functional test sequences,"
Journal of Electronic Testing: Theory and Applications(JETTA), Vol. 26, No. 2, pp.151-164, Apr. 2010.
BibTeX
[120]Tomokazu Yoneda, Akiko Shuto, Hideyuki Ichihara, Tomoo Inoue and Hideo Fujiwara,
"Design and optimization of transparency-based TAM for soc test,"
IEICE Transactions on Information and Systems, Vol. E93-D, No. 6, pp.1549-1559, June 2010.
BibTeX
IEICE
[121]Hiroshi Iwata, Satoshi Ohtake and Hideo Fujiwara,
"A method of path mapping from RTL to gate level and its application to false path identification,"
IEICE Trans. on Information and Systems, Vol. E93-D, No. 7, pp.1857-1865, July 2010.
BibTeX
IEICE
[122]藤原 克哉, 藤原 秀雄, オビエン・ マリー・エンジェリン, 玉本 英夫,
"セキュアスキャン設計のためのシフトレジスタ等価回路の列挙と合成 ,"
電子情報通信学会和文論文誌D-I, Vol. J93-D, No. 11, pp.2426-2436, Nov. 2010.
BibTeX
IEICE
[123]Marie Engelene J. Obien, Satoshi Ohtake and Hideo Fujiwara,
"F-scan: a DFT method for functional scan at RTL,"
IEICE Trans. on Information and Systems, Vol. E94-D, No. 1, pp.104-113, Jan. 2011.
BibTeX
IEICE
[124]Michiko Inoue, Tomokazu Yoneda, Muneo Hasegawa and Hideo Fujiwara,
"Balanced secure scan: partial scan approach for secret information protection,"
Journal of Electronic Testing: Theory and Applications(JETTA), To Appear.
BibTeX
[125]Norlina Paraman, Chia Yee Ooi, Ahmad Zuri Sha'ameri and Hideo Fujiwara,
"A new class of easily testable assignment decision diagram,"
Malaysian Journal Computer Science (MJCS), Vol. 23, No. 1, pp.1-17, To Appear.
BibTeX

会議録
[1]Tomoo Inoue, Tomonori Yonezawa and Hideo Fujiwara,
"An optimal scheme of parallel processing for test generation in a distributed system,"
2nd IEEE Asian Test Symposium, pp.8-13, Nov. 1993.
BibTeX
[2]Michiko Inoue, Wei Chen, Toshimitsu Masuzawa and Nobuki Tokura,
"Linear-time snapshot using multi-writer multi-reader registers,"
8th International Workshop on Distributed Algorithms(Lecture Notes in Computer Science 857, Springer-Verlag), Terschelling, The Netherlands, pp.130-140, 1994.
BibTeX
[3]Tomoo Inoue, Takaharu Fujii and Hideo Fujiwara,
"On the performance analysis of parallel processing for test generation,"
3rd IEEE Asian Test Symposium, pp.69-74, Nov. 1994.
BibTeX
[4]Akihiro Fujiwara, Toshimitsu Masuzawa and Hideo Fujiwara,
"An optimal parallel algorithm for the Euclidean distance maps of binary images,"
First IEEE Internatinal Conference on Algorithms and Architecture for Parallel Processing, 1995.
BibTeX
[5]Tomoo Inoue, Hironori Maeda and Hideo Fujiwara,
"A scheduling problem in test generation,"
IEEE VLSI Test Symposium, pp.344-349, Apr. 1995.
BibTeX
[6]Toshimitsu Masuzawa,
"A fault-tolerant and self-stabilizing protocol for the topology problem,"
2nd Workshop on Self-Stabilizing Systems, Las Begas, NV, pp.1.1-1.15, May 1995.
BibTeX
[7]Tomoo Inoue, Hideo Fujiwara, Hiroyuki Nichinishi, Tokumi Yokohira and Takuji Okamoto,
"Universal test complexity of field-programmable gate arrays,"
4th IEEE Asian Test Symposium, pp.259-265, Nov. 1995.
BibTeX
[8]Yasurou Satou, Michiko Inoue, Toshimitsu Masuzawa and Hideo Fujiwara,
"A snapshot algorithm for distributed mobile systems,"
16th International Conference on Distributed Computing Systems, pp.734-743, 1996.
BibTeX
[9]Akihiro Fujiwara, Michiko Inoue, Toshimitsu Masuzawa and Hideo Fujiwara,
"A simple parallel algorithm for the medial axis transform of binary images,"
IEEE Second International Conference on Algorithms & Architectures for Paralle Processing, pp.1-8, 1996.
BibTeX
[10]Tomoo Inoue, Toshimitsu Masuzawa, Hiroshi Youra and Hideo Fujiwara,
"An approach to the synthesis of synchronizable finite state machines with partial scan,"
Fifth IEEE Asian Test symposium, pp.130-135, Nov. 1996.
BibTeX
[11]Hiroyuki Nichinishi, Tokumi Yokohira, Takuji Okamoto, Tomoo Inoue and Hideo Fujiwara,
"A test methodology for interconnect structures of LUT-based FPGAs,"
Fifth IEEE Asian Test symposium, pp.68-74, Nov. 1996.
BibTeX
[12]Katuyuki Takabatake, Michiko Inoue, Toshimitsu Masuzawa and Hideo Fujiwara,
"Non-scan design for testable data paths using thru operation,"
Asia and South Pacific Design Automation Conference, pp.313-318, Jan. 1997.
BibTeX
[13]Akihiro Fujiwara, Michiko Inoue, Toshimitsu Masuzawa and Hideo Fujiwara,
"A parallel algorithm for weighted distance transforms,"
11th International Parallel Processing Symposium, pp.407-412, Apr. 1997.
BibTeX
[14]Eiichiou Ueda, Yoshiaki Katayama, Toshimitsu Masuzawa and Hideo Fujiwara,
"A latency-optimal superstabilizing mutual exclusion protocol,"
3rd Workshop on self-stabilizing systems, pp.110-124, Aug. 1997.
BibTeX
[15]Michiko Inoue, Sen Moriya, Toshimitsu Masuzawa and Hideo Fujiwara,
"Optimal wait-free clock synchronization protocol on a shared-memory multi-processor system,"
the 11th International Workshop on Distributed Algorithms (LNCS 1320), pp.290-304, Sep. 1997.
BibTeX
[16]Tomoo Inoue, Satoshi Miyazaki and Hideo Fujiwara,
"On the complexity of universal fault diagnosis for look-up table FPGAs,"
Sixth IEEE Asian Test Symp., pp.276-281, Nov. 1997.
BibTeX
[17]Hiroyuki Nichinishi, Tokumi Yokohira, Takuji Okamoto, Tomoo Inoue and Hideo Fujiwara,
"Testing for the programming circuit of LUT-based FPGAs,"
Sixth IEEE Asian Test Symp., pp.242-247, Nov. 1997.
BibTeX
[18]Satoshi Ohtake, Tomoo Inoue and Hideo Fujiwara,
"Sequential test generation based on circuit pseudo-transformation,"
Sixth IEEE Asian Test Symp., pp.62-67, Nov. 1997.
BibTeX
[19]Tomoya Takasaki, Tomoo Inoue and Hideo Fujiwara,
"Partial scan design methods based on internally balanced structure,"
Asia and South Pacific Design Automation Conference, pp.211-216, Feb. 1998.
BibTeX
[20]Akihiro Fujiwara, Michiko Inoue and Toshimitsu Masuzawa,
"A parallel algorithm for euclidean distance transforms on the mesh,"
the 1998 International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA'98), pp.1726-1733, July 1998.
BibTeX
[21]Michiko Inoue, Takeshi Higashimura, Kenji Noda, Toshimitsu Masuzawa and Hideo Fujiwara,
"A high-level synthesis method for weakly testable data paths,"
IEEE the 7th Asian Test Symposium (ATS'98), pp.40-45, Dec. 1998.
BibTeX
[22]Tomoo Inoue, Toshinori Hosokawa, Takahiro Mihara and Hideo Fujiwara,
"An optimal time expansion model based on combinational ATPG for RT level circuits,"
IEEE the 7th Asian test symposium (ATS'98), pp.190-197, Dec. 1998.
BibTeX
[23]Satoshi Ohtake, Toshimitsu Masuzawa and Hideo Fujiwara,
"A non-scan DFT method for controllers to achieve complete fault efficiency,"
IEEE the 7th Asian test symposium (ATS'98), pp.204-211, Dec. 1998.
BibTeX
[24]Sen Moriya, Michiko Inoue, Toshimitsu Masuzawa and Hideo Fujiwara,
"Self-stabilizing wait-free clock synchronization with bounded space,"
the 2nd International Conference on Princeples of Distrubuted Systems, pp.129-143, Dec. 1998.
BibTeX
[25]Kunihiko Hayashi, Michiko Inoue, Toshimitsu Masuzawa and Hideo Fujiwara,
"A layout adjustment algorithm for disjoint rectangles preserving orthogonal order,"
Sixth Symposium on Graph Drawing (LNCS 1574), pp.183-197, Jan. 1999.
BibTeX
[26]Hiroki Wada, Toshimitsu Masuzawa, Kewal K. Saluja and Hideo Fujiwara,
"A DFT method for RTL deta paths achieving 100% fault efficiency under hierachical test environment,"
IEEE European Test Workshop, May 1999.
BibTeX
[27]Akihiro Fujiwara, Takashi Ishimizu, Michiko Inoue, Toshimitsu Masuzawa and Hideo Fujiwara,
"Parallel selection algorithms for CGM and BSP with application to sorting,,"
Joint Symposium on Parallel Processing, pp.261-268, June 1999.
BibTeX
[28]石水 隆, 藤原 暁宏, 井上 美智子, 増澤 利光, 藤原 秀雄,
"2値画像上の全最近点を求めるBSPモデル上の並列アルゴリズム ,"
並列処理シンポジウム, pp.253-260, June 1999.
BibTeX
[29]Akihiro Fujiwara, Hirokazu Katsuki, Michiko Inoue and Toshimitsu Masuzawa,
"Parallel selection algorithms with analysis on clusters,"
Proceedings of 1999 International Symposium on Parallel Architectures, Algorithm, and Networks I-SPAN'99, pp.388-393, June 1999.
BibTeX
[30]Takashi Ishimizu, Akihiro Fujiwara, Michiko Inoue, Toshimitsu Masuzawa and Hideo Fujiwara,
"Parallel algorithms for all nearest neighbors of binary images on the BSP model,"
Proceedings of 1999 International Symposium on Parallel Architectures, Algorithms, and Networks I-SPAN'99, pp.394-399, June 1999.
BibTeX
[31]Tomoya Takasaki, Tomoo Inoue and Hideo Fujiwara,
"A high-level synthesis approach to partial scan design,"
IEEE the 8th Asian Test Symposium (ATS'99), pp.309-314, Nov. 1999.
BibTeX
[32]Debesh K. Das, Satoshi Ohtake and Hideo Fujiwara,
"New DFT techniques of non-scan sequential circuits with complete fault efficiency,"
IEEE the 8th Asian test symposium(ATS'99), pp.263-268, Nov. 1999.
BibTeX
[33]Satoshi Ohtake, Michiko Inoue and Hideo Fujiwara,
"A method of test generation for weakly testable data paths using test knowledge extracted from RTL description,"
IEEE the 8thAsian test symposium (ATS'99), pp.5-12, Nov. 1999.
BibTeX
[34]Toshinori Hosokawa, Tomoo Inoue, Toshihiro Hiraoka and Hideo Fujiwara,
"Static and dynamic test sequence compaction methods for acyclic sequential circuits using a time expasion model,"
Proceedings of the Eighth Asian Test Symposium, pp.193-199, Nov. 1999.
BibTeX
[35]Sen Moriya, Katsuro Suda, Michiko Inoue, Toshimitsu Masuzawa and Hideo Fujiwara,
"Wait-free linearizable distributed shared memory,"
Proceedings of the IASTED Internaitonal Conference on Parallel and Distributed Computing and Systems (PDCS'99), pp.335-342, Nov. 1999.
BibTeX
[36]Hideo Fujiwara,
"A new definition and a new class of sequential circuits with combinational test generation complexity,"
13th International Conference on VLSI Design, pp.288-293, Jan. 2000.
BibTeX
[37]Hiroki Wada, Toshimitsu Masuzawa, Kewal K. Saluja and Hideo Fujiwara,
"Design for strong testability of RTL data paths to provide complete fault efficiency,"
13th International Conference on VLSI Design, pp.300-305, Jan. 2000.
BibTeX
[38]Satoshi Ohtake, Hiroki Wada, Toshimitsu Masuzawa and Hideo Fujiwara,
"A non-scan DFT method at register-transfer level to achieve complete fault efficiency,"
Asia and South Pacific Design Automation Conference 2000 (ASP-DAC2000), pp.599-604, Jan. 2000.
BibTeX
[39]Emil Gizdarski and Hideo Fujiwara,
"A new data structure for SAT-based static learning with impact on test generation,"
Digest of IEEE European Test Workshop (ETW 2000), pp.313-314, May 2000.
BibTeX
[40]Akihiro Fujiwara, Michiko Inoue and Toshimitsu Masuzawa,
"Parallelizability of some P-complete problems,"
Proceedings of, pp.116-122, May 2000.
BibTeX
[41]Satoshi Ohtake, Shintaro Nagai, Hiroki Wada and Hideo Fujiwara,
"A DFT method at RTL based on fixed-control testability to achieve 100% fault efficiency,"
Workshop on RTL ATPG & DFT 2000 (WRTLT2000), Sep. 2000.
BibTeX
[42]Dong Xiang, Yi Xu and Hideo Fujiwara,
"Non-scan design for testability for synchronous sequential circuits based on conflict analysis,"
International Test Conference, pp.520-529, Oct. 2000.
BibTeX
[43]Tomoo Inoue, Debesh K. Das, Takahiro Mihara, Chiiho Sano and Hideo Fujiwara,
"Test generation for acyclic sequential circuits with hold registers,"
ICCAD, pp.550-556, Nov. 2000.
BibTeX
[44]Michiko Inoue, Emil Gizdarski and Hideo Fujiwara,
"A class of sequential circuits with combinational test generation complexity under single-fault assumption,"
Proceedings of the Ninth Asian Test Symposium (ATS2000), pp.398-403, Dec. 2000.
BibTeX
[45]Toshimitsu Masuzawa, Minoru Idutu, Hiroki Wada and Hideo Fujiwara,
"Single-control testablity of RTL data paths for BIST,"
Proceedings of the Ninth Asian Test Symposium (ATS2000), pp.210-215, Dec. 2000.
BibTeX
[46]X. Li, Toshimitsu Masuzawa and Hideo Fujiwara,
"Strong self-testability for data paths high-level synthesis,"
Proceedings of the Ninth Asian Test Symposium(ATS2000), pp.229-234, Dec. 2000.
BibTeX
[47]Emil Gizdarski and Hideo Fujiwara,
"SPIRIT: satisfiabiliy problem implementation for redundancy identification,"
the Ninth Asian Test Symposium (ATS2000), pp.171-178, Dec. 2000.
BibTeX
[48]Michiko Inoue, Shinya Umetani, Toshimitsu Masuzawa and Hideo Fujiwara,
"Adaptive long-lived o(k^2)-renaming with o(k^2) steps,"
15th International Symposium on Distributed Computing (LNCS2180), pp.123-135, 2001.
BibTeX
Abstract
[49]Satoshi Ohtake, Shintaro Nagai, Hiroki Wada and Hideo Fujiwara,
"A DFT method for RTL circuits to achieve complete fault efficiency based on fixed-control testability,"
Asia and South Pacific Design Automation Conference 2001(ASP-DAC2001), pp.331-334, 2001.
BibTeX
[50]Debesh K. Das, Bhargab B. Bhattacharya, Satoshi Ohtake and Hideo Fujiwara,
"Testable design of sequential circuits with improved fault efficiency,"
VLSI Design 2001, pp.128-133, Jan. 2001.
BibTeX
[51]Emil Gizdarski and Hideo Fujiwara,
"SPIRIT: a high robust combinational test generation algorithm,"
19th IEEE VLSI Test Symposium, Los Angeles, CA, USA, pp.346-351, Apr. 2001.
BibTeX
[52]Emil Gizdarski and Hideo Fujiwara,
"A framework on low complexity static learning,"
38th Design Automation Conference, Las Vegas Convention Center, pp.546-549, June 2001.
BibTeX
[53]Tomokazu Yoneda and Hideo Fujiwara,
"Design for consecutive testability of systems-on-a-chip with built-in self testable cores,"
IEEE 2001 Workshop on RTL ATPG & DFT (WRTLT'01), pp.28-37, Nov. 2001.
BibTeX
[54]Md. Altaf-Ul-Amin, Satoshi Ohtake and Hideo Fujiwara,
"Design for hierarchical two-pattern testability of data paths,"
IEEE the 10th Asian test symposium, pp.11-16, Nov. 2001.
BibTeX
[55]Ken-ichi Yamaguchi, Hiroki Wada, Toshimitsu Masuzawa and Hideo Fujiwara,
"A BIST method based on concurrent single-control testability of RTL data paths,"
IEEE the 10th Asian test symposium, pp.313-318, Nov. 2001.
BibTeX
[56]Tomokazu Yoneda and Hideo Fujiwara,
"A DFT method for core-based systems-on-a-chip based on consecutive testability,"
IEEE the 10th Asian test symposium 2001 (ATS'01), pp.193-198, Nov. 2001.
BibTeX
[57]Shintaro Nagai, Satoshi Ohtake and Hideo Fujiwara,
"A design for hierarchical testability for RTL data paths using extended data flow graphs,"
Workshop on RTL ATPG and DFT (WRTLT2001), pp.128-133, Nov. 2001.
BibTeX
Abstract
[58]Emil Gizdarski and Hideo Fujiwara,
"Fault set partition for efficient width compression ,"
Digest of 7th IEEE European Test Workshop, pp.13-14, May 2002.
BibTeX
[59]Erik Larsson and Hideo Fujiwara,
"Power constrained preemptive TAM scheduling,"
Digest of 7th IEEE European Test Workshop, pp.411-416, May 2002.
BibTeX
[60]Erik Larsson and Hideo Fujiwara,
"Power constrained preemptive TAM scheduling,"
Formal of 7th IEEE European Test Workshop, pp.26-29, May 2002.
BibTeX
[61]Satoshi Ohtake, Shunjiro Miwa and Hideo Fujiwara,
"A method of test generation for path delay faults in balanced sequential circuits,"
VLSI Test Symposium 2002, pp.321-327, May 2002.
BibTeX
[62]Michiko Inoue, Chikateru Jinno and Hideo Fujiwara,
"An extended class of sequential circuits with combinational test generation complexity,"
Proceedings of 2002 IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2002), pp.200-205, Sep. 2002.
BibTeX
[63]Tomokazu Yoneda and Hideo Fujiwara,
"Design for consecutive transparency of RTL circuits,"
Digest of Papers, IEEE 3rd Workshop on RTL and High Level Testing (WRTLT'02), pp.18-23, Nov. 2002.
BibTeX
[64]Erik Larsson and Hideo Fujiwara,
"Optimal test access mechanism scheduling using preemption and reconfigurable wrappers,"
Digest of Papers, IEEE 3rd Workshop on RTL and High Level Testing (WRTLT'02), pp.6-11, Nov. 2002.
BibTeX
[65]Ken-ichi Yamaguchi, Michiko Inoue and Hideo Fujiwara,
"Hierarchical BIST: test-per-clock BIST with low overhead,"
Digest of Papers, IEEE 3rd Workshop on RTL and High Level Testing (WRTLT'02), pp.42-47, Nov. 2002.
BibTeX
[66]Tomoo Inoue and Hideo Fujiwara,
"A partial scan design with orthogonal scan paths,"
Digest of Papers, IEEE 3rd Workshop on RTL and High Level Testing (WRTLT'02), pp.38-41, Nov. 2002.
BibTeX
[67]Md. Altaf-Ul-Amin, Satoshi Ohtake and Hideo Fujiwara,
"Design for two-pattern testability of controller-data path circuits,"
IEEE the 11th Asian Test Symposium (ATS'02), pp.73-79, Nov. 2002.
BibTeX
[68]Dong Xiang, Shan Gu and Hideo Fujiwara,
"Non-scan design for testability based on fault-oriented conflict analysis,"
IEEE the 11th Asian Test Symposium (ATS'02), pp.86-91, Nov. 2002.
BibTeX
[69]Tomoo Inoue, Tomokazu Miura, Akio Tamura and Hideo Fujiwara,
"A scheduling method in high-level synthesis for acyclic partial scan design,"
IEEE the 11th Asian Test Symposium (ATS'02), pp.128-133, Nov. 2002.
BibTeX
[70]Emil Gizdarski and Hideo Fujiwara,
"Fault set partition for efficient width compression,"
IEEE the 11th Asian Test Symposium (ATS'02), pp.194-199, Nov. 2002.
BibTeX
[71]Erik Larsson , Klas Arvidsson, Hideo Fujiwara and Zebo Peng,
"Integrated test scheduling, test parallelization and TAM design,"
IEEE the 11th Asian Test Symposium (ATS'02), pp.397-404, Nov. 2002.
BibTeX
[72]Satoshi Ohtake, Kouhei Ohtani and Hideo Fujiwara,
"A method of test generation for path delay faults using stuck-at fault test generation algorithms,"
Design Automation and Test in Europe 2003 (DATE03), pp.310-315, Mar. 2003.
BibTeX
[73]Erik Larsson and Hideo Fujiwara,
"Test resource partitioning and optimization for SOC designs,"
Proc. 21st IEEE VLSI Test Symposium (VTS'03), pp.319-324, Apr. 2003.
BibTeX
[74]Tomokazu Yoneda and Hideo Fujiwara,
"Design for consecutivetransparency of cores in system-on-a-chip,"
Proc. 21st IEEE VLSI Test Symposium 2003 (VTS'03), pp.287-292, Apr. 2003.
BibTeX
[75]Tsuyoshi Iwagaki, Satoshi Ohtake and Hideo Fujiwara,
"A path delay test generation method for sequential circuits based on reducibility to combinational test generation,"
Digest of Papers 8th IEEE European Test Workshop (ETW '03), pp.307-312, May 2003.
BibTeX
[76]Michiko Inoue, Kazuhiro Suzuki, Hiroyuki Okamoto and Hideo Fujiwara,
"Test synthesis for datapaths using datapath-controller functions,"
Digest of Papers of European Test Workshop (ETW2003), pp.207-208, May 2003.
BibTeX
[77]Tomokazu Yoneda, Tetsuo Uchiyama and Hideo Fujiwara,
"Area and time co-optimization for system-on-a-chip based on consecutive testability,"
IEEE International Test Conference 2003 (ITC'03), pp.415-422, Sep. 2003.
BibTeX
[78]Tsuyoshi Iwagaki, Satoshi Ohtake and Hideo Fujiwara,
"An approach to non-scan design for delay fault testability of controllers,"
Digest of Papers IEEE the 4th Workshop on RTL and High Level Testing (WRTLT '03), pp.79-85, Nov. 2003.
BibTeX
[79]Hao Wu, Zhiqiang You, Michiko Inoue and Hideo Fujiwara,
"Test length minimization under power constraints for combinational circuits,"
IEEE 4th Workshop on RTL and High Level Testing (WRTLT'03), pp.125-127, Nov. 2003.
BibTeX
[80]Zhiqiang You, Michiko Inoue and Hideo Fujiwara,
"On the non-scan BIST schemes under power constraints for RTL data paths,"
IEEE 4th Workshop on RTL and High Level Testing (WRTLT'03), pp.14-21, Nov. 2003.
BibTeX
[81]Erik Larsson and Hideo Fujiwara,
"Optimal system-on-chip test scheduling,"
IEEE the 12th Asian Test Symposium (ATS '03), pp.306-311, Nov. 2003.
BibTeX
[82]Dong Xiang, Ming-Jing Chen, Jia-guang Sun and Hideo Fujiwara,
"Improving test quality of scan-based BIST by scan chain partitioning,"
IEEE the 12th Asian Test Symposium (ATS '03), pp.12-17, Nov. 2003.
BibTeX
[83]Dong Xiang, Shan Gu and Hideo Fujiwara,
"Non-scan design for testability for mixed RTL circuits with both data paths and controller via conflict analysis,"
IEEE the 12th Asian Test Symposium (ATS '03), pp.300-303, Nov. 2003.
BibTeX
[84]Masahide Miyazaki, Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka and Hideo Fujiwara,
"A DFT selection method for reducing test application time of system-on-chips,"
IEEE the 12th Asian Test Symposium (ATS '03), pp.412-417, Nov. 2003.
BibTeX
[85]Toshinori Hosokawa, Hiroshi Date, Masahide Miyazaki, Michiaki Muraoka and Hideo Fujiwara,
"A method of test plan grouping to shorten test length for RTL data paths under a test controller area constraint,"
IEEE the 12th Asian Test Symposium (ATS '03), pp.130-135, Nov. 2003.
BibTeX
[86]Virendra Singh, Michiko Inoue, Kewal K. Saluja and Hideo Fujiwara,
"Software-based delay fault testing of processor cores,"
IEEE the 12th Asian Test Symposium (ATS '03), pp.68-71, Nov. 2003.
BibTeX
[87]Michiko Inoue, Kazuhiro Suzuki, Hiroyuki Okamoto and Hideo Fujiwara,
"Test synthesis for datapaths using datapath-controller functions,"
IEEE the 12th Asian Test Symposium (ATS '03), pp.294-299, Nov. 2003.
BibTeX
[88]Tsuyoshi Iwagaki, Satoshi Ohtake and Hideo Fujiwara,
"Reducibility of sequential test generation to combinational test generation for several delay fault models,"
Proc. IEEE the 12th Asian Test Symposium (ATS '03), pp.58-63, Nov. 2003.
BibTeX
[89]Virendra Singh, Michiko Inoue, Kewal K. Saluja and Hideo Fujiwara,
"Instruction-based delay fault self-testing of processor cores,"
International Conference on VLSI Design 2004, pp.933-938, Jan. 2004.
BibTeX
[90]Yannick Bonhomme, Tomokazu Yoneda, Hideo Fujiwara and Patrick Girard,
"An efficient scan tree design for test time reduction,"
9th IEEE European Test Symposium (ETS'04), pp.174-179, May 2004.
BibTeX
[91]Tsuyoshi Iwagaki, Satoshi Ohtake and Hideo Fujiwara,
"A design methodology to realize delay testable controllers using state transition information,"
Proc. 9th IEEE European Test Symposium (ETS '04), pp.168-173, May 2004.
BibTeX
[92]Zhiqiang You, Ken-ichi Yamaguchi, Michiko Inoue, Jacob Savir and Hideo Fujiwara,
"Power-constrained test scheduling for RTL datapaths of non-scan BIST schemes,"
IEEE 13th Asian Test Symposium (ATS'04), pp.32-39, Nov. 2004.
BibTeX
[93]Kazuko Kambe, Michiko Inoue and Hideo Fujiwara,
"Efficient template generation for instruction-based self-test of processor cores,"
IEEE 13th Asian Test Symposium (ATS'04), pp.152-157, Nov. 2004.
BibTeX
[94]Chia Yee Ooi and Hideo Fujiwara,
"Classification of sequential circuits based on tau**k notation,"
IEEE 13th Asian Test Symposium (ATS'04), pp.348-353, Nov. 2004.
BibTeX
[95]Debesh K. Das, Tomoo Inoue, Susanta Chakraborty and Hideo Fujiwara,
"Max-testable class of sequential circuits having combinational test generation complexity,"
IEEE 13th Asian Test Symposium (ATS'04), pp.342-347, Nov. 2004.
BibTeX
[96]Yoshiyuki Nakamura, Jacob Savir and Hideo Fujiwara,
"Defect level vs. yield and fault coverage in the presence of an imperfect BIST,"
IEEE 5th Workshop on RTL and High Level Testing (WRTLT'04), pp.79-84, Nov. 2004.
BibTeX
[97]Yuusuke Saga, Tomokazu Yoneda and Hideo Fujiwara,
"Serial and parallel TAM designs for system-on-chip interconnects based on 2-pattern testability,"
IEEE 5th Workshop on RTL and High Level Testing (WRTLT'04), pp.13-18, Nov. 2004.
BibTeX
[98]Michiko Inoue, Kazuko Kambe, Naotaka Hoashi and Hideo Fujiwara,
"Instruction-based self-test for sequeintial modules in processors,"
IEEE 5th Workshop on RTL and High Level Testing (WRTLT'04), pp.109-114, Nov. 2004.
BibTeX
[99]Mariane Comte, Satoshi Ohtake, Hideo Fujiwara and Michel Renovell,
"Electrical analysis of a domino logic cell with GOS faults,"
IEEE International Workshop on Current & Defect Based Testing 2005, 2005.
BibTeX
[100]Patrick Girard, Tomokazu Yoneda, Hideo Fujiwara and Yannick Bonhomme,
"Test application time reduction with a dynamically reconfigurable scan tree architecture,"
8th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS'05), pp.19-26, Apr. 2005.
BibTeX
[101]Mariane Comte, Satoshi Ohtake, Hideo Fujiwara and Michel Renovell,
"Electrical behavior of GOS faults in domino logic,"
The 8th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS), pp.210-215, Apr. 2005.
BibTeX
[102]Virendra Singh, Michiko Inoue, Kewal K. Saluja and Hideo Fujiwara,
"Program-based testing of super-scalar microprocessors,"
IEEE 14th North Atlantic Test Workshop (NATW'05), pp.79-86, May 2005.
BibTeX
[103]Virendra Singh, Michiko Inoue, Kewal K. Saluja and Hideo Fujiwara,
"Instruction-based delay fault self-testing of pipelined processor cores,"
IEEE International Symposium on Circuits and Systems (ISCAS'05), pp.5686-5689, May 2005.
BibTeX
[104]Tsuyoshi Iwagaki, Satoshi Ohtake and Hideo Fujiwara,
"Acceleration of transition test generation for acyclic sequential circuits utilizing constrained combinational stuck-at test generation,"
Proc. 10th IEEE European Test Symposium (ETS '05), pp.48-53, May 2005.
BibTeX
[105]Zhiqiang You, Tsuyoshi Iwagaki, Michiko Inoue and Hideo Fujiwara,
"A low power deterministic test using scan chain disable technique,"
IEEE 6th Workshop on RTL and High Level Testing (WRTLT'05), pp.184-191, July 2005.
BibTeX
[106]Thomas Clouqueur, Kewal K. Saluja and Hideo Fujiwara,
"Matrices of multiple weights for test response compaction with unknown values,"
IEEE 6th Workshop on RTL and High Level Testing (WRTLT'05), pp.24-30, July 2005.
BibTeX
[107]Yoshiyuki Nakamura, Thomas Clouqueur, Kewal K. Saluja and Hideo Fujiwara,
"Perfect erro identification in at-speed BIST environment,"
IEEE 6th Workshop on RTL and High Level Testing (WRTLT'05), pp.1-11, July 2005.
BibTeX
[108]Masato Nakazato, Satoshi Ohtake and Hideo Fujiwara,
"Acceleration of test generation for sequential circuits using knowledge obtained from synthesis for testability,"
IEEE 6th Workshop on RTL and High Level Testing (WRTLT'05), pp.50-60, July 2005.
BibTeX
[109]Chia Yee Ooi, Thomas Clouqueur and Hideo Fujiwara,
"Test generation complexity for path delay faults based on tau^k-notation,"
IEEE 6th Workshop on RTL and High Level Testing (WRTLT'05), pp.61-72, July 2005.
BibTeX
[110]Masahide Miyazaki, Tomokazu Yoneda and Hideo Fujiwara,
"A memory grouping method for reducing memory BIST logic of system-on-chips,"
IEEE 6th Workshop on RTL and High Level Testing (WRTLT'05), pp.31-37, July 2005.
BibTeX
[111]Toshinori Hosokawa and Hideo Fujiwara,
"A functional test method for state observable FSMs,"
IEEE 6th Workshop on RTL and High Level Testing (WRTLT'05), pp.123-130, July 2005.
BibTeX
[112]Dong Xiang, Kai-wei Li and Hideo Fujiwara,
"Localizing test power consumption for scan testing,"
IEEE 6th Workshop on RTL and High Level Testing (WRTLT'05), pp.18-23, July 2005.
BibTeX
[113]Thomas Clouqueur, Kamran Zarrineh, Kewal K. Saluja and Hideo Fujiwara,
"Design and analysis of multiple weight linear compactors of resonses containing unknown values,"
IEEE International Test Conference 2005 (ITC 2005), pp.1099-1108, Nov. 2005.
BibTeX
[114]Tomokazu Yoneda, Hisakazu Takakuwa and Hideo Fujiwara,
"Power-constrained area and time co-optimization for socs based on consecutive testability,"
IEEE the 14th Asian Test Symposium (ATS'05), pp.150-155, Dec. 2005.
BibTeX
[115]Thomas Clouqueur, Kewal K. Saluja and Hideo Fujiwara,
"A class of linear space compactors for enhanced diganosis,"
IEEE the 14th Asian Test Symposium (ATS'05), pp.260-265, Dec. 2005.
BibTeX
[116]Hiroyuki Iwata, Tomokazu Yoneda, Satoshi Ohtake and Hideo Fujiwara,
"A DFT method for RTL data paths based on partially strong testability to guarantee complete fault efficiency,"
IEEE the 14th Asian Test Symposium (ATS'05), pp.306-311, Dec. 2005.
BibTeX
[117]Yuki Yoshikawa, Satoshi Ohtake, Michiko Inoue and Hideo Fujiwara,
"Design for testability based on single-port-change delay testing for data paths,"
IEEE the 14th Asian Test Symposium (ATS'05), pp.254-259, Dec. 2005.
BibTeX
[118]Kazuko Kambe, Tsuyoshi Iwagaki, Michiko Inoue and Hideo Fujiwara,
"Efficient constraint extraction for template-based processor self-test generation,"
IEEE the 14th Asian Test Symposium (ATS'05), pp.444-447, Dec. 2005.
BibTeX
[119]Dong Xiang, Ming-Jing Chen and Hideo Fujiwara,
"Using weighted test signals to improve the effectiveness of scan-based BIST,"
IEEE the 14th Asian Test Symposium (ATS'05), pp.126-131, Dec. 2005.
BibTeX
[120]Dong Xiang, Kai-wei Li and Hideo Fujiwara,
"Design for cost-effective scan testing by reconfiguring scan flip-flops,"
IEEE the 14th Asian Test Symposium (ATS'05), pp.318-321, Dec. 2005.
BibTeX
[121]Hideyuki Ichihara, Naoki Okamoto, Tomoo Inoue, Toshinori Hosokawa and Hideo Fujiwara,
"An effective design for hierarchical test generation based on strong testability,"
IEEE the 14th Asian Test Symposium (ATS'05), pp.288-293, Dec. 2005.
BibTeX
[122]Masahide Miyazaki, Tomokazu Yoneda and Hideo Fujiwara,
"A memory grouping method for sharing memory BIST logic,"
11th Asia and South Pacific Design Automation Conference(ASP-DAC2006), pp.671-676, Jan. 2006.
BibTeX
[123]Michel Renovell, Mariane Comte, Satoshi Ohtake and Hideo Fujiwara,
"Electrical behavior of GOS fault affected domino logic cell,"
Third IEEE International Workshop on Electronic Design, Test & Applications (DELTA 2006) , pp.183-189, Jan. 2006.
BibTeX
[124]Ilia Polian and Hideo Fujiwara,
"Functional constraints vs. test compression in scan-based delay testing,"
Design, Automation and Test in Europe 2006 (DATE'06), pp.1039-1044, Mar. 2006.
BibTeX
[125]Tomokazu Yoneda, Kimihiko Masuda and Hideo Fujiwara,
"Power-constrained test scheduling for multi-clock domain socs,"
Design, Automation and Test in Europe 2006 (DATE'06), pp.297-302, Mar. 2006.
BibTeX
[126]Yuki Yoshikawa, Satoshi Ohtake and Hideo Fujiwara,
"An approach to reduce over-testing of path delay faults in data paths using RT-level information,"
Digest of Papers, 11th IEEE European Test Symposium (ETS'06), pp.146-151, May 2006.
BibTeX
[127]Zhiqiang You, Michiko Inoue and Hideo Fujiwara,
"Extended compatibilities for scan tree construction,"
Digest of Papers, 11th IEEE European Test Symposium (ETS'06), pp.13-18, May 2006.
BibTeX
[128]Thomas Clouqueur, Kamran Zarrineh, Kewal K. Saluja and Hideo Fujiwara,
"Diagnosis in designs with block compactors,"
Digest of Papers, 11th IEEE European Test Symposium (ETS'06), pp.199-204, May 2006.
BibTeX
[129]Yoshiyuki Nakamura, Jacob Savir and Hideo Fujiwara,
"BIST pretest of ICs: risks and benefits,"
IEEE 24th VLSI Test Symposium (VTS'06), pp.142-147, May 2006.
BibTeX
[130]Dong Xiang, Kai-wei Li, Hideo Fujiwara and Jia-guang Sun,
"Generating compact robust and non-robust tests for complete coverage of path delay faults based on stuck-at tests,"
24th IEEE International Conference on Computer Design (ICCD'06), pp.446-451, Oct. 2006.
BibTeX
[131]Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orailoglu and Hideo Fujiwara,
"Power-constrained SOC test schedules through utilization of functional buses,"
24th IEEE International Conference on Computer Design (ICCD'06), pp.230-236, Oct. 2006.
BibTeX
[132]Chia Yee Ooi and Hideo Fujiwara,
"A new class of sequential circuits with acyclic test generation complexity,"
24th IEEE International Conference on Computer Design (ICCD'06), pp.425-431, Oct. 2006.
BibTeX
[133]Tsuyoshi Iwagaki, Satoshi Ohtake and Hideo Fujiwara,
"A new test generation model for broadside transition testing of partial scan circuits,"
IFIP International Conference on Very Large Scale Integration (VLSI-SoC 2006), pp.308-313, Oct. 2006.
BibTeX
[134]Ilia Polian, Bernd BECKER, Masato Nakazato, Satoshi Ohtake and Hideo Fujiwara,
"Low-cost hardening of image processing applications against soft errors systems (DFT'06),"
The 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI, pp.274-279, Oct. 2006.
BibTeX
[135]Chia Yee Ooi and Hideo Fujiwara,
"A new scan design technique based on pre-synthesis thru functions,"
15th IEEE Asian Test Symposium (ATS'06), pp.163-168, Nov. 2006.
BibTeX
[136]Masato Nakazato, Satoshi Ohtake, Michiko Inoue and Hideo Fujiwara,
"Design for testability of software-based self-test for processors,"
15th IEEE Asian Test Symposium (ATS'06), pp.375-380, Nov. 2006.
BibTeX
[137]Yoshiyuki Nakamura, Thomas Clouqueur, Kewal K. Saluja and Hideo Fujiwara,
"Diagnosing at-speed scan BIST circuits using a low speed and low memory tester,"
15th IEEE Asian Test Symposium (ATS'06), pp.409-414, Nov. 2006.
BibTeX
[138]Dong Xiang, Krishnendu Chakrabarty , Jia-guang Sun and Hideo Fujiwara,
"Compressing test data for deterministic BIST using a reconfigurable scan architecture,"
15th IEEE Asian Test Symposium (ATS'06), pp.299-304, Nov. 2006.
BibTeX
[139]Thomas Edison Yu, Tomokazu Yoneda, Danella Zhao and Hideo Fujiwara,
"Designing power-aware wrapper for multi-clock domain cores using clock domain partitioning,"
IEEE 7th Workshop on RTL and High Level Testing (WRTLT'06), pp.43-48, Nov. 2006.
BibTeX
[140]Hiroyuki Iwata, Tomokazu Yoneda and Hideo Fujiwara,
"A new non-scan DFT method based on the time expansion model for RTL controller-datapath circuits,"
IEEE 7th Workshop on RTL and High Level Testing (WRTLT'06), pp.7-12, Nov. 2006.
BibTeX
[141]Tomokazu Yoneda, Akiko Shuto, Hideyuki Ichihara, Tomoo Inoue and Hideo Fujiwara,
"An optimal test bus design for transparency-based soc test,"
IEEE 7th Workshop on RTL and High Level Testing (WRTLT'06), pp.21-26, Nov. 2006.
BibTeX
[142]Zhiqiang You, Michiko Inoue and Hideo Fujiwara,
"Extended compatibilities for scan tree construction,"
IEEE 7th Workshop on RTL and High Level Testing (WRTLT'06), pp.75-80, Nov. 2006.
BibTeX
[143]Toshinori Hosokawa, Ryoichi Inoue and Hideo Fujiwara,
"Fault dependent/independent test generation methods for state observable FSMs,"
IEEE 7th Workshop on RTL and High Level Testing (WRTLT'06), pp.13-18, Nov. 2006.
BibTeX
[144]Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orailoglu and Hideo Fujiwara,
"Core-based testing of multiprocessor system-on-chips utilizing hierarchical functional buses,"
12th Asia and South Pacific Design Automation Conference 2007 (ASP-DAC'07), pp.720-725, Jan. 2007.
BibTeX
[145]Danella Zhao, Unni Chandran and Hideo Fujiwara,
"Shelf packing to the design and optimization of a power-aware multi-frequency wrapper architecture for modular IP cores,"
12th Asia and South Pacific Design Automation Conference 2007 (ASP-DAC'07), pp.714-719, Jan. 2007.
BibTeX
[146]Tomokazu Yoneda, Masahiro Imanishi and Hideo Fujiwara,
"An soc test scheduling algorithm using reconfigurable union wrappers,"
Design, Automation and Test in Europe (DATE'07), pp.231-236, Apr. 2007.
BibTeX
[147]Fawnizu Azmadi Hussin, Tomokazu Yoneda and Hideo Fujiwara,
"Optimization of noc wrapper design under bandwidth and test time constraints,"
12th IEEE European Test Symposium (ETS'07), pp.35-40, May 2007.
BibTeX
[148]Danella Zhao, Ronghua Huang, Tomokazu Yoneda and Hideo Fujiwara,
"Power-aware multi-frequency heterogeneous soc test framework design with floor-ceiling packing,"
2007 IEEE International Symposium on Circuits and Systems (ISCAS 2007), pp.2942-2945, May 2007.
BibTeX
[149]Thomas Edison Yu, Tomokazu Yoneda, Danella Zhao and Hideo Fujiwara,
"Using domain partitioning in wrapper design for IP cores under power constraints,"
IEEE 25th VLSI Test Symposium (VTS'07), pp.369-374, May 2007.
BibTeX
[150]Tomokazu Yoneda, Akiko Shuto, Hideyuki Ichihara, Tomoo Inoue and Hideo Fujiwara,
"TAM design and optimization for transparency-based soc test,"
IEEE 25th VLSI Test Symposium (VTS'07), pp.381-386, May 2007.
BibTeX
[151]Satoshi Ohtake, Kosuke Yabuki and Hideo Fujiwara,
"Delay testing for application-specific interconnects of FPGAs based on inphase structure,"
The IEEE European Test Symposium 2007, pp.131-136, May 2007.
BibTeX
[152]Hiroyuki Iwata, Tomokazu Yoneda and Hideo Fujiwara,
"A DFT method for time expansion model at register transfer level,"
44th Design Automation Conference (DAC'07), pp.682-687, June 2007.
BibTeX
[153]Dong Xiang, Yang Zhao, Kai-wei Li and Hideo Fujiwara,
"Fast fault simulation for path delay faults based on logic simulation and selected testable paths,"
2007 IEEE International Test Conference (ITC 07), pp.707-716, Oct. 2007.
BibTeX
[154]Nobuya Oka, Chia Yee Ooi, Hideyuki Ichihara, Tomoo Inoue and Hideo Fujiwara,
"An extended class of acyclically testable circuits,"
8th IEEE Workshop on RTL and High Level Testing (WRTLT'07), pp.17-22, Oct. 2007.
BibTeX
[155]Yuki Yoshikawa, Satoshi Ohtake and Hideo Fujiwara,
"RTL don't care path identification and synthesis for transforming don't care paths into false paths,"
8th IEEE Workshop on RTL and High Level Testing (WRTLT'07), pp.9-15, Oct. 2007.
BibTeX
[156]Ryoichi Inoue, Toshinori Hosokawa and Hideo Fujiwara,
"A test generation method for state observable FSMs to increase defect coverage under the test length constraint,"
Digest of Papers IEEE 8th Workshop on RTL and High Level Testing (WRTLT'07), pp.79-86, Oct. 2007.
BibTeX
[157]Fawnizu Azmadi Hussin, Tomokazu Yoneda and Hideo Fujiwara,
"Area overhead and test time co-optimization through noc bandwidth sharing,"
IEEE 16th Asian Test Symposium (ATS'07), pp.459-462, Oct. 2007.
BibTeX
[158]Yuki Yoshikawa, Satoshi Ohtake and Hideo Fujiwara,
"False path identification using RTL information and its application to over-testing reduction for delay faults,"
IEEE 16th Asian Test Symposium (ATS'07), pp.65-68, Oct. 2007.
BibTeX
[159]Tomokazu Yoneda, Yusuke Fukuda and Hideo Fujiwara,
"Test scheduling for memory cores with built-in self-repair ,"
IEEE 16th Asian Test Symposium (ATS'07), pp.199-204, Oct. 2007.
BibTeX
[160]Toshinori Hosokawa, Ryoichi Inoue and Hideo Fujiwara,
"Fault-dependent/independent test generation methods for state observable FSMs ,"
IEEE 16th Asian Test Symposium (ATS'07), pp.275-278, Oct. 2007.
BibTeX
[161]Danella Zhao, Ronghua Huang and Hideo Fujiwara,
"Power-conscious multi-frequency modular testing of socs with dynamic reconfiguration of multi-port ATE,"
IEEE 16th Asian Test Symposium (ATS'07), pp.107-110, Oct. 2007.
BibTeX
[162]Dong Xiang, Krishnendu Chakrabarty , Dianwei Hu and Hideo Fujiwara,
"Scan testing for complete coverage of path delay faults with reduced test data volume, test application time, and hardware,"
IEEE 16th Asian Test Symposium (ATS'07), pp.329-334, Oct. 2007.
BibTeX
[163]Thomas Edison Yu, Tomokazu Yoneda, Krishnendu Chakrabarty and Hideo Fujiwara,
"Thermal-safe test access mechanism and wrapper co-optimization for system-on-chip,"
IEEE 16th Asian Test Symposium(ATS'07), pp.187-192, Oct. 2007.
BibTeX
[164]Tsuyoshi Iwagaki, Satoshi Ohtake, Mineo Kaneko and Hideo Fujiwara,
"Efficient path delay test generation based on stuck-at test generation using checker circuitry,"
IEEE/ACM International Conference on Computer-Aided Design (ICCAD'07), pp.418-423, Nov. 2007.
BibTeX
[165]Tsuyoshi Iwagaki and Satoshi Ohtake,
"Generation of power-constrained scan tests and its difficulty,"
IEEE International Design and Test Workshop, Dec. 2007.
BibTeX
[166]Yu HU, Xiang FU, Xiaoxin FAN and Hideo Fujiwara,
"Localized random access scan: towards low area and routing overhead,,"
13th Asia and South Pacific Design Automation Conference (ASP-DAC'08), pp.565-570, Jan. 2008.
BibTeX
[167]Tomokazu Yoneda and Hideo Fujiwara,
"Wrapper and TAM co-optimization for reuse of soc functional interconnects,"
Design, Automation and Test in Europe (DATE'08), pp.1366-1369, Mar. 2008.
BibTeX
[168]Elena Hammari, Michiko Inoue, Einar J. Aas and Hideo Fujiwara,
"Delay test of FPGA routing networks by branched test paths,"
Informal Digest of Papers, 13th IEEE European Test Symposium (ETS'08), May 2008.
BibTeX
[169]Satoshi Ohtake and Kewal K. Saluja,
"A systematic scan insertion technique for asynchronous on-chip interconnects,"
Workshop on Low Power Design Impact on Test and Reliability (LPonTR), May 2008.
BibTeX
[170]Hiroshi Iwata, Satoshi Ohtake and Hideo Fujiwara,
"An approach to RTL-GL path mapping based on functional equivalence,"
9th IEEE Workshop on RTL and High Level Testing (WRTLT'08), pp.63-68, Nov. 2008.
BibTeX
[171]Takashi Yoshida, Tomokazu Yoneda and Hideo Fujiwara,
"A reconfigurable wrapper design for multi-clock domain cores,"
9th IEEE Workshop on RTL and High Level Testing (WRTLT'08), pp.13-18, Nov. 2008.
BibTeX
[172]Hideo Fujiwara, Chia Yee Ooi and Yuki Shimizu,
"Enhancement of test environment generation for assignment decision diagrams,"
9th IEEE Workshop on RTL and High Level Testing (WRTLT'08), pp.45-50, Nov. 2008.
BibTeX
[173]Jaan Raik, Hideo Fujiwara and Anna Krivenko,
"RT-level identification of potentially testable initialization faults,"
9th IEEE Workshop on RTL and High Level Testing (WRTLT'08), pp.57-62, Nov. 2008.
BibTeX
[174]Norlina Paraman, Chia Yee Ooi, Ahmad Zuri Sha'ameri and Hideo Fujiwara,
"A new class of easily testable assignment decision diagram,"
9th IEEE Workshop on RTL and High Level Testing (WRTLT'08), pp.51-56, Nov. 2008.
BibTeX
[175]Thomas Edison Yu, Tomokazu Yoneda, Satoshi Ohtake and Hideo Fujiwara,
"Identifying non-robust untestable RTL paths in circuits with multi-cycle paths,"
Proc. of IEEE the 17th Asian Test Symposium (ATS'08), pp.125-130, Nov. 2008.
BibTeX
[176]Ryoichi Inoue, Toshinori Hosokawa and Hideo Fujiwara,
"A test generation method for state-observable FSMs to increase defect coverage under the test length constraint,"
Proc. of IEEE the 17th Asian Test Symposium (ATS'08), pp.27-34, Nov. 2008.
BibTeX
[177]Jaan Raik, Hideo Fujiwara, Raimund Ubar and Anna Krivenko,
"Untestable fault identification in sequential circuits using model-checking,"
Proc. of IEEE the 17th Asian Test Symposium(ATS'08), pp.21-26, Nov. 2008.
BibTeX
[178]Yuki Yoshikawa, Satoshi Ohtake, Tomoo Inoue and Hideo Fujiwara,
"Fast false path identification based on functional unsensitizability using RTL information,"
14th Asia and South Pacific Design Automation Conference 2009 (ASP-DAC'09), pp.660-665, Jan. 2009.
BibTeX
[179]Thomas Edison Yu, Tomokazu Yoneda, Krishnendu Chakrabarty and Hideo Fujiwara,
"Test infrastructure design for core-based system-on-chip under cycle-accurate thermal constraints,"
14th Asia and South Pacific Design Automation Conference 2009 (ASP-DAC'09), pp.793-798, Jan. 2009.
BibTeX
[180]Satoshi Ohtake, Naotsugu Ikeda, Michiko Inoue and Hideo Fujiwara,
"Unsensitizable path identification at RTL using high-level synthesis information,"
16th IEEE International Test Synthesis Workshop (ITSW 2009), Mar. 2009.
BibTeX
[181]Yuki Yoshikawa, Satoshi Ohtake, Tomoo Inoue and Hideo Fujiwara,
"A synthesis method to alleviate over-testing of delay faults based on RTL don't care path identification,"
IEEE VLSI Test Symposium (VTS '09), May 2009.
BibTeX
[182]Michiko Inoue, Tomokazu Yoneda, Muneo Hasegawa and Hideo Fujiwara,
"Partial scan approach for secret information protection,"
Proceedings of the 14th IEEE European Test Symposium(ETS'09), pp.143-148, May 2009.
BibTeX
[183]Michiko Inoue, Tsuyoshi Suzuki and Hideo Fujiwara,
"Acceleration by contention for shared memory mutual exclusion algorithms,"
Proceedings of the 23rd International Symposium on Distributed Computing, pp.172-173, Sep. 2009.
BibTeX
[184]Marie Engelene J. Obien and Hideo Fujiwara,
"F-scan: an approach to functional RTL scan for assignment decision diagrams,"
IEEE 8th International Conference on ASIC (ASICON2009), pp.589-592, Oct. 2009.
BibTeX
[185]Zhiqiang You, Jiedi Huang, Michiko Inoue, Jishun Kuang and Hideo Fujiwara,
"A response compactor for extended compatibility scan tree construction,"
IEEE 8th International Conference on ASIC (ASICON2009), pp.609-612, Oct. 2009.
BibTeX
[186]Yasuo Sato, Seiji Kajihara, Yukiya Mimura, Tomokazu Yoneda, Satoshi Ohtake, Michiko Inoue and Hideo Fujiwara,
"A circuit failure prediction mechanism (DART) for high field reliability,"
Proc. IEEE 8th International Conference on ASIC (ASICON2009), pp.581-584, Oct. 2009.
BibTeX
[187]Jaynarayan T. Tudu, Erik Larsson , Virendra Singh and Hideo Fujiwara,
"Scan cell reordering to minimize peak power during scan testing of soc,"
10th IEEE Workshop on RTL and High Level Testing (WRTLT'09), pp.43-48, Nov. 2009.
BibTeX
[188]Michiko Inoue, Satoshi Ohtake, Yuichi Uemoto and Hideo Fujiwara,
"Path-based resource binding to reduce delay fault test cost,"
10th IEEE Workshop on RTL and High Level Testing (WRTLT'09), pp.29-32, Nov. 2009.
BibTeX
[189]Marie Engelene J. Obien and Hideo Fujiwara,
"A DFT method for functional scan at RTL,"
10th IEEE Workshop on RTL and High Level Testing (WRTLT'09), pp.6-15, Nov. 2009.
BibTeX
[190]Hongxia Fang, Krishnendu Chakrabarty and Hideo Fujiwara,
"Observation-point selection at register-transfer level to increase defect coverage for functional test sequences,"
Digest of Papers of the 10th IEEE Workshop on RTL and High Level Testing (WRTLT2009), pp.16-22, Nov. 2009.
BibTeX
[191]Hongxia Fang, Krishnendu Chakrabarty and Hideo Fujiwara,
"RTL DFT techniques to enhance defect coverage for functional test sequences,"
IEEE International High Level Design Validation and Test Workshop 2009 (IEEE HLDVT 2009), pp.160-165, Nov. 2009.
BibTeX
[192]Hideo Fujiwara and Marie Engelene J. Obien,
"Secure and testable scan design using extended de bruijn graphs,"
15th Asia and South Pacific Design Automation Conference (ASP-DAC 2010), pp.413-418, Jan. 2010.
BibTeX
[193]Raghavendra Adiga, Arpit Gandhi, Virendra Singh, Kewal K. Saluja, Hideo Fujiwara and Adit D. Singh,
"On minimization of test application time for RAS,"
23rd Internaional Conference on VLSI Design, pp.293-398, Jan. 2010.
BibTeX
[194]Michiko Inoue, Akira Taketani, Tomokazu Yoneda, Hiroshi Iwata and Hideo Fujiwara,
"Optimizing delay test quality with a limited size of test set,"
IEEE International Workshop on Reliability Aware System Design and Test (RASDAT'10), pp.46-51, Jan. 2010.
BibTeX
[195]Hiroshi Iwata, Satoshi Ohtake and Hideo Fujiwara,
"Enabling false path identification from RTL for reducing design and test futileness,"
The 5th IEEE International Symposium on Electronic Design, Test & Applications (DELTA 2010), pp.20-25, Jan. 2010.
BibTeX
[196]Satoshi Ohtake, Naotsugu Ikeda, Michiko Inoue and Hideo Fujiwara,
"A method of unsensitizable path identification using high level design information,"
Conference: International conference on Design & Technology of Integrated Systems in nanoscale era (DTIS2010) , Mar. 2010.
BibTeX
[197]Katsuya Fujiwara, Hideo Fujiwara, Marie Engelene J. Obien and Hideo Tamamoto,
"SREEP: shift register equivalents enumeration and synthesis program for secure scan design,"
13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2010), pp.193-196, Apr. 2010.
BibTeX
[198]Tomokazu Yoneda, Michiko Inoue, Yasuo Sato and Hideo Fujiwara,
"Thermal-uniformity aware x-filling to reduce temperature-induced delay variation for accurate at-speed testing,"
28th IEEE VLSI Test Symposium (VTS'10), pp.188-193, Apr. 2010.
BibTeX
[199]Satoshi Ohtake, Hiroshi Iwata and Hideo Fujiwara,
"A synthesis method to propagate false path information from RTL to gate level,"
The IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems 2010, pp.197-200, Apr. 2010.
BibTeX
[200]Jaynarayan T. Tudu, Erik Larsson , Virendra Singh and Hideo Fujiwara,
"Graph theoretical approach for scan cell reordering to minimize peak shift power,"
ACM Great Lake Symposium on VLSI (GLSVLSI 2010), pp.73-78, May 2010.
BibTeX
[201]Michiko Inoue, Akira Taketani, Tomokazu Yoneda, Hiroshi Iwata and Hideo Fujiwara,
"Test pattern selection to optimize delay test quality with a limited size of test set,"
IEEE European Test Symposium (ETS'10), pp.260, May 2010.
BibTeX
[202]Hyunbean Yi, Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Seiji Kajihara and Hideo Fujiwara,
"Aging test strategy and adaptive test scheduling for soc failure prediction,"
IEEE International On-Line Testing Symposium (IOLTS'10), pp.21-26, July 2010.
BibTeX
[203]Marie Engelene J. Obien, Satoshi Ohtake and Hideo Fujiwara,
"Delay fault ATPG for f-scannable RTL circuits,"
IEEE International Symposium on Communications and Information Technologies(ISCIT'10), pp.717-722, Oct. 2010.
BibTeX
[204]Marie Engelene J. Obien, Satoshi Ohtake and Hideo Fujiwara,
"Constrained ATPG for functional RTL circuits using f-scan,"
2010 IEEE International Test Conference, pp.(Paper 21.1) 1-10, Nov. 2010.
BibTeX
[205]Alodeep Sanyal, Krishnendu Chakrabarty , Mahmut Yilmaz and Hideo Fujiwara,
"RT-level design-for-testability and expansion of functional test sequences for enhanced defect coverage,"
2010 IEEE International Test Conference, Nov. 2010.
BibTeX
[206]Katsuya Fujiwara, Hideo Fujiwara and Hideo Tamamoto,
"SREEP-2: SR-Equivalent generator for secure and testable scan design,"
11th IEEE Workshop on RTL and High Level Testing (WRTLT'10), pp.7-12, Dec. 2010.
BibTeX
[207]Chia Yee Ooi and Hideo Fujiwara,
"Functional fault model for micro operation faults of high correlation with stuck-at faults,"
11th IEEE Workshop on RTL and High Level Testing (WRTLT'10), pp.139-144, Dec. 2010.
BibTeX
[208]Maksim Jenihhin, Jaan Raik, Hideo Fujiwara, Raimund Ubar and Taavi Viilukas,
"An approach for verification assertions reuse in RTL test pattern generation,"
11th IEEE Workshop on RTL and High Level Testing (WRTLT'10), pp.107-110, Dec. 2010.
BibTeX
[209]Fawnizu Azmadi Hussin, Thomas Edison Yu, Tomokazu Yoneda and Hideo Fujiwara,
"RedSOCs-3d: thermal-safe test scheduling for 3d-stacked soc,"
2010 Asia Pacific Conference on Circuits and Systems (APCCAS 2010), Dec. 2010.
BibTeX
[210]Hiroshi Iwata, Satoshi Ohtake, Michiko Inoue and Hideo Fujiwara,
"Bipartite full scan design: a DFT method for asynchronous circuits,"
IEEE 19th Asian Test Symposium (ATS2010), pp.206-211, Dec. 2010.
BibTeX
[211]Tomokazu Yoneda, Michiko Inoue, Akira Taketani and Hideo Fujiwara,
"Seed ordering and selection for high quality delay test,"
IEEE 19th Asian Test Symposium (ATS2010), pp.313-318, Dec. 2010.
BibTeX
[212]Zhiqiang You, Jiedi Huang, Michiko Inoue, Jishun Kuang and Hideo Fujiwara,
"Capture in turn scan for reduction of test data volume, test application time and test power,"
IEEE 19th Asian Test Symposium (ATS2010) , pp.371-374, Dec. 2010.
BibTeX
[213]Hideo Fujiwara, Katsuya Fujiwara and Hideo Tamamoto,
"Secure scan design using shift register equivalents against differential behavior attack,"
16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011), pp.818-823, Jan. 2011.
BibTeX
[214]Tomokazu Yoneda, Makoto Nakao, Michiko Inoue, Yasuo Sato and Hideo Fujiwara,
"A test pattern optimization to reduce spatial and temporal temperature variations,"
IEEE International Workshop on Reliability Aware System Design and Test (RASDAT'11), pp.7-12, Jan. 2011.
BibTeX
[215]Tomokazu Yoneda, Makoto Nakao, Michiko Inoue, Yasuo Sato and Hideo Fujiwara,
"Temperature-variation aware test pattern optimization,"
IEEE European Test Symposium (ETS'11), May 2011.
BibTeX

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BibTeX
[39]東村 剛嗣, 井上 美智子, 藤原 秀雄,
"弱可検査性のための設計目標を利用したデータパス高位合成 ,"
信学技報 (FTS97-64), Dec. 1997.
BibTeX
[40]大堀 力, 井上 美智子, 増澤 利光, 藤原 秀雄,
"分散移動システムにおける前後関係保存放送プロトコル ,"
信学技報 (COMP97-79), pp.9-16, Jan. 1998.
BibTeX
[41]三原 隆宏, 井上 智生, 藤原 秀雄,
"L/H 型レジスタを有する無閉路順序回路のテスト生成法,"
信学技報 (FTS97-75), pp.33-40, Feb. 1998.
BibTeX
[42]Akihiro Fujiwara, Takashi Ishimizu, Michiko Inoue, Toshimitsu Masuzawa and Hideo Fujiwara,
"Parallel selection algorithms for CGM and BSP with application to sorting,"
Technical Report of IEICE (COMP97-103), Mar. 1998.
BibTeX
[43]守屋 宣, 井上 美智子, 増澤 利光, 藤原 秀雄,
"共有メモリシステムにおける同期時間最適な自己安定無待機時計合わせプロトコル ,"
信学技報 (COMP98-18), June 1998.
BibTeX
[44]細川 利典, 井上 智生, 平岡 敏洋, 藤原 秀雄,
"時間展開モデルを用いた無閉路順序回路のテスト系列圧縮について ,"
信学技報 (VLD98-287), Sep. 1998.
BibTeX
[45]石水 隆, 藤原 暁宏, 井上 美智子, 増澤 利光, 藤原 秀雄,
"2値画像上の全最近点を求めるBSPモデル上の並列アルゴリズム ,"
信学技報 (COMP98-42), Oct. 1998.
BibTeX
[46]高崎 智也, 井上 智生, 藤原 秀雄,
"無閉路部分スキャン設計を指向したデータパスのテスト容易化高位合成 ,"
信学技報 (FTS98-114), pp.65-72, Dec. 1998.
BibTeX
[47]Debesh K. Das, Satoshi Ohtake and Hideo Fujiwara,
"New DFT techniques of non-scan sequential circuits with complete fault efficiency,"
Technical Report of IEICE (FTS98-115), pp.73-80, Dec. 1998.
BibTeX
[48]須田 克郎, 守屋 宣, 井上 美智子, 増澤 利光, 藤原 秀雄,
"線形化可能性を保証する共有オブジェクトの無待機な実現 ,"
信学技報 (COMP98-73), pp.9-16, Jan. 1999.
BibTeX
[49]寺田 雅人, 井上 美智子, 増澤 利光, 藤原 秀雄,
"分散移動システムにおける全域チェックポイントについて ,"
信学技報 (COMP98-74), pp.17-24, Jan. 1999.
BibTeX
[50]大坪 裕, 井上 智生, 福井 祥光, 藤原 秀雄,
"内臓プロセッサを利用したマイクロコントローラのテスト高速化に関する考察 ,"
情処研報 (DA91-4), pp.25-32, Feb. 1999.
BibTeX
[51]佐野 ちいほ, 井上 智生, Debesh K. Das, 藤原 秀雄,
"ホールド機能を考慮した順序回路のテスト容易化設計法 ,"
情処研報 (DA91-7), pp.43-50, Feb. 1999.
BibTeX
[52]Satoshige Ukena, Yoshiaki Katayama, Toshimitsu Masuzawa and Hideo Fujiwara,
"A self-stabilizing k-exclusion protocol with k-wait-freedom,"
Technical Report of IEICE (COMP98-87), pp.33-40, Mar. 1999.
BibTeX
[53]守屋 宣, 須田 克郎, 井上 美智子, 増澤 利光, 藤原 秀雄,
"線形化可能性を保証する分散共有メモリの無待機な実現 ,"
信学技報 (COMP99-37), pp.45-52, Sep. 1999.
BibTeX
[54]Akihiro Fujiwara, Michiko Inoue and Toshimitsu Masuzawa,
"Practical parallelizability of some P-complete problems,"
IPSJ SIG Notes, Vol. 99-AL-69, pp.9-16, Sep. 1999.
BibTeX
[55]大竹 哲史, 和田 弘樹, 増澤 利光, 藤原 秀雄,
"完全故障検出効率を保証するレジスタ転送レベルでの非スキャンテスト容易化設計法 ,"
信学技報, (VLD99-81, ICD99-210, FTS99-59), pp.47-54, Nov. 1999.
BibTeX
[56]永井 慎太郎, 和田 弘樹, 大竹 哲史, 藤原 秀雄,
"固定制御可検査性に基づく RTL 回路の非スキャンテスト容易化設計法,"
信学技報 (VLD99-101), pp.29-36, Jan. 2000.
BibTeX
[57]井筒 稔, 和田 弘樹, 増澤 利光, 藤原 秀雄,
"単一制御可検査性に基づくレジスタ転送レベルデータパスの組込み自己テスト容易化設計法 ,"
信学技法 (FTS99-78), pp.23-30, Feb. 2000.
BibTeX
[58]長谷川 学, 浮穴 学慈, 片山 喜章, 増澤 利光, 藤原 秀雄,
"ヒープ順序づき木を構成する自己安定プロトコル ,"
信学技報 (COMP99-79), pp.1-8, Mar. 2000.
BibTeX
[59]谷口 博人, 井上 美智子, 増澤 利光, 藤原 秀雄,
"アドホックネットワークにおけるクラスタ構成法 ,"
信学技報 (COMP99-80), pp.9-16, Mar. 2000.
BibTeX
[60]Emil Gizdarski and Hideo Fujiwara,
"A new data structure for SAT-based static learning with impact on test generation,"
Technical report of IEICE (VLD2000-11), pp.81-88, Apr. 2000.
BibTeX
[61]井上 美智子, Emil Gizdarski, 藤原 秀雄,
"単一故障仮定のもとで組合せテスト生成複雑度をもつ順序回路のクラス ,"
信学技報 (FTS2000-70, VLD2000-105, ICD2000-162), Vol. 100, No. 473, pp.215-220, Nov. 2000.
BibTeX
[62]Md. Altaf-Ul-Amin, Satoshi Ohtake and Hideo Fujiwara,
"Analyzing path delay fault testability of RTL data paths: a non-scan approach,"
Technical Report of IEICE (FTS2000-71, VLD2000-106, ICD2000-163), Vol. 100, No. 473, pp.221-226, Nov. 2000.
BibTeX
[63]和田 弘樹, 増澤 利光, 藤原 秀雄,
"強可検査性に基づくテスト容易化高位合成 ,"
信学技報 (FTS2000-74, VLD2000-109, ICD2000-166), Vol. 100, No. 473, pp.239-244, Nov. 2000.
BibTeX
[64]Emil Gizdarski and Hideo Fujiwara,
"SPRIT: a high robust combinational test generation algorithm,"
Technical report of IEICE (FTS2000-69, VLD2000-104, ICD2000-161), Vol. 100, No. 473, pp.209-214, Nov. 2000.
BibTeX
[65]米田 友和, 藤原 秀雄,
"連続可検査性に基づくコアベース・システムオンチップのテスト容易化設計法 ,"
信学技報 (FTS2000-75, VLD2000-110, ICD2000-167), Vol. 100, No. 473, pp.245-250, Nov. 2000.
BibTeX
[66]鈴木 和博, 井上 美智子, 藤原 秀雄,
"コントローラの機能を利用したデータパスのテスト容易化設計 ,"
電子情報通信学会技術報告 (FTS2000-86), Feb. 2001.
BibTeX
[67]三輪 俊二郎, 大竹 哲史, 藤原 秀雄,
"組合せテスト生成複雑度でパス遅延故障テスト生成可能な順序回路のクラス ,"
信学技報 (FTS2000), Vol. 100, No. 620, pp.9-16, Feb. 2001.
BibTeX
[68]山口 賢一, 和田 弘樹, 増澤 利光, 藤原 秀雄,
"レジスタ転送レベルデータパスの単一制御並行可検査性に基づく組み込み自己テスト ,"
信学技法 (FTS2001-3), Vol. 101, No. 2, pp.17-24, Apr. 2001.
BibTeX
[69]Shinya Umetani, Michiko Inoue, Toshimitsu Masuzawa and Hideo Fujiwara,
"Adaptive long-lived renaming algorithm in the asynchronous shared memory,"
Technical Report of IPSJ (2001-AL-80-9), pp.59-66, Sep. 2001.
BibTeX
Abstract
[70]浮穴 学慈, 片山 喜章, 増澤 利光, 藤原 秀雄,
"非停止永久故障に耐性を有する自己安定生成木構成プロトコル ,"
電子情報通信学会技術報告(COMP2001-31), pp.17-23, Sep. 2001.
BibTeX
[71]三浦 友和, 井上 智生, 田村 秋雄, 藤原 秀雄,
"無閉路部分スキャン設計を指向した高位合成におけるスケジューリングについて ,"
信学技法(VLD2001-107,ICD2001-152,FTS2001-54), Vol. 101, No. 467, pp.109-114, Nov. 2001.
BibTeX
[72]永井 慎太郎, 大竹 哲史, 藤原 秀雄,
"拡張データフローグラフを用いた RT レベルデータパスの階層テスト容易化設計法,"
信学技報(VLD2001-106,ICD2001-151,FTS2001-53), Vol. 101, No. 467, pp.103-108, Nov. 2001.
BibTeX
Abstract
[73]神野 元彰, 井上 美智子, 藤原 秀雄,
"ホールドとスイッチの機能を考慮した内部平衡構造 ,"
信学技報 (FTS2001-82), Vol. 101, No. 658, pp.37-44, Feb. 2002.
BibTeX
Abstract
[74]岡本 絋征, 井上 美智子, 藤原 秀雄,
"レジスタ転送レベル回路に対するテストプラン埋め込み型テスト容易化設計法 ,"
信学技報(FTS2001-83), Vol. 101, No. 658, pp.45-52, Feb. 2002.
BibTeX
Abstract
[75]岩垣 剛, 大竹 哲史, 藤原 秀雄,
"不連続再収斂構造に基づくパス遅延故障に対する部分拡張スキャン設計法 ,"
信学技報 (FTS2001-84), Vol. 101, No. 658, pp.53-60, Feb. 2002.
BibTeX
[76]Md. Altaf-Ul-Amin, Satoshi Ohtake and Hideo Fujiwara,
"Design for two-pattern testability of controller-data path circuits,"
Technical Report of IEICE (FTS2002), Vol. 101, No. 658, pp.61-67, Feb. 2002.
BibTeX
[77]大谷 浩平, 大竹 哲史, 藤原 秀雄,
"縮退故障のテスト生成アルゴリズムを用いたパス遅延故障に対するテスト生成法 ,"
信学技報 (FTS2002), Vol. 101, No. 658, pp.69-75, Feb. 2002.
BibTeX
[78]井上 美智子, 大竹 哲史, 藤原 秀雄,
"完全スキャン設計と等価な部分スキャン設計 ,"
電子情報通信学会総合大会2002年総合大会講演論文集, Vol. SD-2-10, Mar. 2002.
BibTeX
[79]大竹 哲史, 井上 美智子, 藤原 秀雄,
"上流からのテスト容易化設計 ,"
電子情報通信学会総合大会2002年総合大会講演論文集, Vol. SD-2-11, Mar. 2002.
BibTeX
Abstract
[80]Tomokazu Yoneda and Hideo Fujiwara,
"Design for consecutive transparency of RTL circuits,"
Technical Report of IEICE (VLD2002-85, ICD2002-129, DC2002-37), Vol. 102, No. 476, pp.19-24, Nov. 2002.
BibTeX
[81]Ken-ichi Yamaguchi, Michiko Inoue and Hideo Fujiwara,
"Hierarchical BIST: test-per-clock BIST with low overhead,"
Technical Report of IEICE (VLD2002-87, ICD2002-131, DC2002-39), Vol. 102, No. 476, pp.29-34, Nov. 2002.
BibTeX
[82]内山 哲夫, 米田 友和, 藤原 秀雄,
"連続可検査性に基づくシステムオンチップの面積オーバヘッドとテスト実行時間の相互最適化 ,"
信学技報 (DC2002-82), Vol. 102, No. 658, pp.19-24, Feb. 2003.
BibTeX
[83]永井 慎太郎, 大竹 哲史, 藤原 秀雄,
"テスト実行時間削減のためのデータパスの強可検査性に基づくテスト容易化設計法 ,"
信学技報(DC2002-84), Vol. 102, No. 658, pp.31-36, Feb. 2003.
BibTeX
[84]Virendra Singh, Michiko Inoue, Kewal K. Saluja and Hideo Fujiwara,
"Program-based delay fault self-testing of processor cores,"
Technical Report of IEICE (DC2003-37), Vol. 103, No. 476, pp.19-24, Nov. 2003.
BibTeX
[85]Tsuyoshi Iwagaki, Satoshi Ohtake and Hideo Fujiwara,
"A method of design for delay fault testability of controllers,"
Technical Report of IEICE (DC2003-38), Vol. 103, No. 476, pp.25-30, Nov. 2003.
BibTeX
[86]Chia Yee Ooi and Hideo Fujiwara,
"Classification of sequential circuits based on combinational test generation complexity,"
Technical Report of IEICE (DC2003-101), Vol. 103, No. 668, pp.67-72, Feb. 2004.
BibTeX
[87]神戸 和子, 井上 美智子, 藤原 秀雄,
"データフローを考慮したプロセッサ自己テストのためのテンプレート生成 ,"
信学技報 (DC2003-95), Vol. 103, No. 668, pp.29-34, Feb. 2004.
BibTeX
[88]帆足 尚孝, 神戸 和子, 井上 美智子, 藤原 秀雄,
"プロセッサ自己テストのためのコントローラ入力時相空間制約 ,"
信学技報 (DC2003-96), Vol. 103, No. 668, pp.35-40, Feb. 2004.
BibTeX
[89]高桑 寿一, 米田 友和, 藤原 秀雄,
"消費電力を考慮した連続可検査性に基づくシステムオンチップの面積オーバヘッドとテスト実行時間の相互最適化 ,"
信学技報(DC2003-99), Vol. 103, No. 668, pp.55-60, Feb. 2004.
BibTeX
[90]嵯峨 佑介, 米田 友和, 藤原 秀雄,
"システムオンチップのインターコネクトに対する2パターン可検査化設計 ,"
信学技報 (DC2004-10), Vol. 104, No. 130, pp.7-12, June 2004.
BibTeX
[91]中村 芳行, 藤原 秀雄,
"BISTの故障を考慮した故障検出率と市場不良率の関係 ,"
信学技報 (DC2004-9), Vol. 104, No. 130, pp.1-6, June 2004.
BibTeX
[92]村田 優, 大竹 哲史, 藤原 秀雄,
"ビット幅調整機能を用いたデータパスのテスト容易化設計法 ,"
信学技報 (DC2004-58), Vol. 104, No. 478, pp.67-72, Dec. 2004.
BibTeX
[93]吉川 祐樹, 大竹 哲史, 井上 美智子, 藤原 秀雄,
"単一端子変化遅延テストに基づくデータパスのテスト容易化設計 ,"
信学技報 (DC2004-58), Vol. 104, No. 478, pp.73-78, Dec. 2004.
BibTeX
[94]横山 真也, 神戸 和子, 井上 美智子, 藤原 秀雄,
"パイプラインプロセッサ自己テストのための命令テンプレート生成 ,"
信学技報 (DC2004-58), Vol. 104, No. 478, pp.61-66, Dec. 2004.
BibTeX
[95]Tsuyoshi Iwagaki, Satoshi Ohtake and Hideo Fujiwara,
"Equivalence of sequential transition test generation and constrained combinational stuck-at test generation,"
Technical Report of IEICE, Vol. 104, No. 664, pp.27-32, Feb. 2005.
BibTeX
[96]今西 真博, 米田 友和, 藤原 秀雄,
"再構成可能結合ラッパーを用いたSoCのテストスケジューリング ,"
信学技報 (DC2004-102), Vol. 104, No. 664, pp.63-68, Feb. 2005.
BibTeX
[97]増田 公彦, 米田 友和, 藤原 秀雄,
"消費電力を考慮したマルチクロックドメインSoCのテストスケジューリング ,"
信学技報 (DC2004-103), Vol. 104, No. 664, pp.69-74, Feb. 2005.
BibTeX
[98]岩田 浩幸, 米田 友和, 大竹 哲史, 藤原 秀雄,
"完全故障検出効率を保証するデータパスの部分強可検査設計 ,"
信学技報 (DC2004-92), Vol. 104, No. 664, pp.1-6, Feb. 2005.
BibTeX
[99]中里 昌人, 大竹 哲史, 藤原 秀雄,
"テスト容易化合成情報に基づく順序回路テスト生成の高速化 ,"
信学技報 (DC2004-97), Vol. 104, No. 664, pp.33-38, Feb. 2005.
BibTeX
[100]矢葺 光佑, 大竹 哲史, 藤原 秀雄,
"同位相構造に基づく特定用途を考慮したFPGA相互接続遅延テスト ,"
電子情報通信学会技術研究報告, Vol. 105, No. 442, pp.1-6, Dec. 2005.
BibTeX
[101]田中 裕, 米田 友和, 藤原 秀雄,
"消費電力を考慮したマルチクロックドメインコアに対する再構成可能ラッパー設計 ,"
信学技報 (VLD2005-63, ICD2005-158, DC2005-40), Vol. 105, No. 442, pp.13-18, Dec. 2005.
BibTeX
[102]Tsuyoshi Iwagaki, Satoshi Ohtake and Hideo Fujiwara,
"A broadside test generation method for transition faults in partial scan circuits,"
IEICE Technical Report (DC2005-54), Vol. 105, No. 443, pp.7-12, Dec. 2005.
BibTeX
[103]山形 信博, 中里 昌人, 神戸 和子, 米田 友和, 大竹 哲史, 井上 美智子, 藤原 秀雄,
"非パイプラインプロセッサの命令レベル自己テストのためのテスト容易化設計 ,"
信学技報 (DC2005-73), Vol. 105, No. 607, pp.7-12, Feb. 2006.
BibTeX
[104]Chia Yee Ooi, Thomas Clouqueur and Hideo Fujiwara,
"A new class of sequential circuits with acyclic test generation complexity,"
Technical Report of IEICE (DC2005-80), Vol. 105, No. 607, pp.49-54, Feb. 2006.
BibTeX
[105]Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orailoglu and Hideo Fujiwara,
"Power-conscious microprocessor-based testing of system-on-chip,"
Technical Report of IEICE (VLD2006-6), Vol. 106, No. 32, pp.25-30, May 2006.
BibTeX
[106]中里 昌人, 大竹 哲史, 井上 美智子, 藤原 秀雄,
"プロセッサの命令レベル自己テストのためのテスト容易化設計 ,"
信学技報 (ICD2006-40〜59), Vol. 106, No. 92, pp.49-54, June 2006.
BibTeX
[107]福田 雄介, 米田 友和, 藤原 秀雄,
"メモリコアに対する組込み自己修復を考慮したSoCのテストスケジューリング ,"
信学技報, Vol. 106, No. 387, pp.59-64, Nov. 2006.
BibTeX
[108]Tsuyoshi Iwagaki, Satoshi Ohtake, Mineo Kaneko and Hideo Fujiwara,
"A test generation framework using checker circuits and its application to path delay test generation,"
Technical Report of IEICE (CAS2006-76), Vol. 106, No. 512, pp.37-42, Jan. 2007.
BibTeX
[109]Yuki Yoshikawa, Satoshi Ohtake and Hideo Fujiwara,
"Reduction in over-testing of delay faults through false paths identification using RTL information,"
IEICE Technical Report (DC2006-87), Vol. 106, No. 528, pp.43-48, Feb. 2007.
BibTeX
[110]Fawnizu Azmadi Hussin, Tomokazu Yoneda and Hideo Fujiwara,
"NoC wrapper optimization under channel bandwidth and test time constraints,"
Technical Report of IEICE (DC2006-80), Vol. 106, No. 528, pp.1-6, Feb. 2007.
BibTeX
[111]Thomas Edison Yu, Tomokazu Yoneda, Danella Zhao and Hideo Fujiwara,
"Power constrained IP core wrapper design with partitioned clock domains,"
Technical Report of IEICE, Vol. 107, No. 101, pp.37-42, June 2007.
BibTeX
[112]Thomas Edison Yu, Tomokazu Yoneda, Krishnendu Chakrabarty and Hideo Fujiwara,
"Thermal-aware test scheduling with cycle-accurate power profiles and test partitioning,"
Technical Report of IEICE (VLD2007-84, DC2007-39(2007-11)), Vol. 107, No. 335, pp.13-18, Nov. 2007.
BibTeX
[113]長谷川 宗士, 井上 美智子, 藤原 秀雄,
"平衡構造を利用した安全なスキャン設計 ,"
信学技報, Vol. 107, No. 482, pp.39-44, Feb. 2008.
BibTeX
[114]池田 直嗣, 大竹 哲史, 井上 美智子, 藤原 秀雄,
"高位合成情報を用いたRTLフォールスパス判定 ,"
信学技報, Vol. 107, No. 482, pp.63-68, Feb. 2008.
BibTeX
[115]岩田 大志, 大竹 哲史, 藤原 秀雄,
"機能等価性情報を用いたRTL-glパスマッピングの一手法 ,"
信学技報 (VLD2008-34), Vol. 108, No. 107, pp.13-18, June 2008.
BibTeX
[116]清水 祐紀, Chia Yee Ooi, 藤原 秀雄,
"ADDを用いたテスト環境生成問題について ,"
信学技報 (VLD2008-35), Vol. 108, No. 107, pp.19-24, June 2008.
BibTeX
[117]吉田 宜司, 米田 友和, 藤原 秀雄,
"マルチクロック・ドメイン・コアテストのための再構成可能ラッパーの一構成法 ,"
信学技報(VLD2008-82, DC2008-50(2008-11)), Vol. 108, No. 298, pp.133-138, Nov. 2008.
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[118]Tsuyoshi Suzuki, Michiko Inoue and Hideo Fujiwara,
"Mutual exclusion algorithm with skipping arbitration tree,"
Technical Report of IPSJ (2009-AL-122), pp.9-16, Jan. 2009.
BibTeX
[119]Hideo Fujiwara and Marie Engelene J. Obien,
"A secure scan design approach using extended de bruijn graph,"
IEICE Technical Report, Vol. 108, No. 431, pp.61-66, Feb. 2009.
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[120]Yuichi Uemoto, Satoshi Ohtake, Michiko Inoue and Hideo Fujiwara,
"Resource binding to minimize the number of RTL paths,"
信学技報(DC2008-77), Vol. 108, No. 431, pp.55-60, Feb. 2009.
BibTeX
[121]Tomokazu Yoneda, Satoshi Ohtake, Michiko Inoue and Hideo Fujiwara,
"An approach to temperature control during VLSI test,"
Proceedings of the IEICE General Conference, Vol. D-10-18, pp.161, Mar. 2009.
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[122]藤原 克哉, 藤原 秀雄, 玉本 英夫,
"セキュアスキャン設計のためのシフトレジスタ等価回路の列挙と合成について ,"
信学技報, Vol. 109, No. 334, pp.13-18, Dec. 2009.
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[123]中尾 良, 米田 友和, 井上 美智子, 藤原 秀雄,
"テスト実行時の温度均一化のためのテストパターン並べ替え法 ,"
信学技報, Vol. 109, No. 416, pp.7-12, Feb. 2010.
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[124]竹谷 啓, 米田 友和, 井上 美智子, 藤原 秀雄,
"BISTにおける高品質遅延故障テストのためのシード選択法 ,"
信学技法, Vol. 109, No. 416, pp.57-62, Feb. 2010.
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[125]Hiroshi Iwata, Satoshi Ohtake, Michiko Inoue and Hideo Fujiwara,
"A full scan design method for asynchronous sequential circuits based on c-element scan paths ,"
IEICE Tech. Rep. (DC2010-8), Vol. 110, No. 106, pp.1-6, June 2010.
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[126]Yasuo Sato, Seiji Kajihara, Michiko Inoue, Tomokazu Yoneda, Satoshi Ohtake, Hideo Fujiwara and Yukiya Mimura,
"Circuit failure prediction by field test (DART) with delay-shift measurement mechanism,"
Technical Report of IEICE(ICDV2010), pp.5-10, Aug. 2010.
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[127]堀 慧悟, 米田 友和, 井上 美智子, 藤原 秀雄,
"高精度遅延テストのためのテストパターン生成法 ,"
信学技法, Vol. 110, No. 413, pp.33-38, Feb. 2011.
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[128]小副川 絵美子, 米田 友和, 井上 美智子, 藤原 秀雄,
"テスト実行時における初期温度均一化のためのパターン生成法 ,"
信学技法, Vol. 110, No. 413, pp.27-32, Feb. 2011.
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解説・総説・コラム
[1]藤原 秀雄,
"テスト生成アルゴリズム ,"
人工知能学会誌, Vol. 8, No. 3, pp.166-172, Mar. 1993.
BibTeX
[2]藤原 秀雄,
"VLSIのテスト ,"
電子情報通信学会誌, Vol. 77, No. 3, pp.288-295, Mar. 1996.
BibTeX
[3]藤原 秀雄,
"テスティング技術論文特集の発行にあたって ,"
電子情報通信学会論文誌(DI), Vol. 79-D-I, No. 12, pp.1007-1008, Dec. 1996.
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[4]Hideo Fujiwara,
"Needed: third-generation ATPG benchmarks,"
The Last Byte, IEEE Design & Test of Computers, Vol. 15, No. 1, Jan.-Mar., pp.96, 1998.
BibTeX
[5]井上 美智子, 藤原 秀雄,
"テスト容易性を考慮したVLSI高位合成:サーベイと今後の動向 ,"
日本信頼性学会誌「信頼性」, Vol. 20, No. 5, pp.333-340, June 1998.
BibTeX
[6]Toshimitsu Masuzawa and Michiko Inoue,
"Fault-tolerance of distributed algorithms: self-stabilization and wait-freedom,"
IEICE Transactions on Information and Systems, Vol. E83-D, No. 3560, pp.550-560, Mar. 2000.
BibTeX
[7]Debesh K. Das, Hideo Fujiwara, Yungang Li, Yinghua Min, Shiyi Xu and Yervant Zorian,
"ATS roundtable: design & test education in asia,"
IEEE Design & Test of Computers, Vol. 21, No. 4, July-Aug., pp.331-338, 2004.
BibTeX
[8]井上 美智子,
"ディペンダブルなVLSIとテスト ,"
日本信頼性学会誌「信頼性」, Vol. 26, No. 4, pp.263-270, June 2004.
BibTeX

著書・編書
[1]藤原 秀雄 (分担執筆),
"新版情報処理ハンドブック(情報処理学会(編)) ,"
オーム社, Nov. 1995.
BibTeX
[2]藤原 秀雄,
"コンピュータ設計概論 ,"
工学図書, Oct. 1998.
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[3]藤原 秀雄 (分担執筆),
"エンサイクロペディア電子情報通信ハンドブック(電子情報通信学会(編)) ,"
オーム社, Nov. 1998.
BibTeX
[4]井上 美智子 (分担執筆),
"アルゴリズム工学 - 計算困難問題への挑戦 -,"
共立出版, June 2001.
BibTeX
[5]藤原 秀雄,
"ディジタルシステムの設計とテスト ,"
工学図書, May 2004.
BibTeX

NAIST テクニカルレポート
[1]Tomoo Inoue, Hironori Maeda and Hideo Fujiwara,
"A scheduling problem in test generation,"
No. 94032, Oct. 1994.
BibTeX
[2]Akihiro Fujiwara, Toshimitsu Masuzawa and Hideo Fujiwara,
"An optimal parallel algorithm for the Euclidean distance maps,"
No. 95014, Mar. 1995.
BibTeX
[3]四浦 洋, 井上 智生, 増澤 利光, 藤原 秀雄,
"部分スキャンによる同期化可能な有限状態機械の合成について ,"
No. 95023, July 1995.
BibTeX
[4]Toshimitsu Masuzawa, Tomoo Inoue, Hiroshi Youra and Hideo Fujiwara,
"One resettable state variable is almost sufficient for synthesizing synchronizable FSMs,"
No. 96014, July 1996.
BibTeX
[5]高崎 智也, 井上 智生, 藤原 秀雄,
"組合せテスト生成可能な拡張部分スキャン設計 ,"
No. 96016, Sep. 1996.
BibTeX
[6]大竹 哲史, 井上 智生, 藤原 秀雄,
"回路疑似変換による順序回路テスト生成の一手法 ,"
No. 96017, Sep. 1996.
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[7]Satoshi Ohtake, Tomoo Inoue and Hideo Fujiwara,
"Sequential test generation based on circuit pseudo-transformation,"
No. 97014, July 1997.
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[8]Tomoo Inoue, Satoshi Miyazaki and Hideo Fujiwara,
"On the complexity of universal fault diagnosis for look-up table FPGAs,"
No. 97020, Oct. 1997.
BibTeX
[9]Tomoya Takasaki, Tomoo Inoue and Hideo Fujiwara,
"Partial scan design methods based on internally balanced structure,"
No. 97022, Nov. 1997.
BibTeX
[10]Toshimitsu Masuzawa, Hiroki Wada, Kewal K. Saluja and Hideo Fujiwara,
"A non-scan DFT method for RTL data paths to achieve complete fault efficiency,"
No. 98009, July 1998.
BibTeX
[11]Debesh K. Das, Satoshi Ohtake and Hideo Fujiwara,
"New DFT techniques of non-scan sequential circuits with complete fault efficiency,"
No. 98013, Nov. 1998.
BibTeX
[12]守屋 宣, 井上 美智子, 増澤 利光, 藤原 秀雄,
"共有メモリマルチプロセッサシステムにおける同期時間最適な無待機時計合わせプロトコル ,"
No. 99004, Mar. 1999.
BibTeX
[13]Tomoo Inoue, Hideo Fujiwara, Hiroyuki Nichinishi, Tokumi Yokohira and Takuji Okamoto,
"Universal test complexity of field-programmable gate arrays,"
No. 99006, Apr. 1999.
BibTeX
[14]Emil Gizdarski and Hideo Fujiwara,
"A new data structure for complete implication graph with application for static learning,"
No. 2000001, Jan. 2000.
BibTeX
[15]Michiko Inoue, Emil Gizdarski and Hideo Fujiwara,
"Theorems for separable primary input faults in internally balanced structures,"
No. 2000004, Mar. 2000.
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[16]Emil Gizdarski and Hideo Fujiwara,
"SPIRIT: satisfiability problem implementation for redundancyidentification and test generation,"
No. 2000005, Apr. 2000.
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[17]Emil Gizdarski and Hideo Fujiwara,
"SPIRIT: a high robust combinational test generation algorithm,"
No. 2000007, Oct. 2000.
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[18]Satoshi Ohtake, Shintaro Nagai, Hiroki Wada and Hideo Fujiwara,
"A non-scan DFT method at RTL based on fixed-control testability to achieve 100% fault efficiency,"
No. 2000009, Nov. 2000.
BibTeX
[19]Emil Gizdarski and Hideo Fujiwara,
"Fault set partition for efficient width compression,"
No. 2001004, Mar. 2001.
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[20]Tomokazu Yoneda and Hideo Fujiwara,
"A DFT method for core-based systems-on-a-chip based on consecutive testability,"
No. 2001006, May 2001.
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[21]永井 慎太郎, 和田 弘樹, 大竹 哲史, 藤原 秀雄,
"固定制御可検査性に基づくRTL回路の非スキャンテスト容易化設計法 ,"
No. 2002002, Jan. 2002.
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Abstract
[22]Erik Larsson and Hideo Fujiwara,
"Preemptive power constrained TAM scheduling for scan-based system-on-chip,"
No. 2002003, Jan. 2002.
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Abstract
[23]岩垣 剛, 大竹 哲史, 藤原 秀雄,
"不連続再収斂順序回路のパス遅延故障に対するテスト生成法 ,"
No. 2002001, Feb. 2002.
BibTeX
[24]神野 元彰, 井上 美智子, 藤原 秀雄,
"ホールドレジスタを含む内部平衡構造 ,"
No. 2002004, Feb. 2002.
BibTeX
[25]Tomokazu Yoneda and Hideo Fujiwara,
"An ILP formulation for consecutive testability of system-on-a-chip,"
No. 2002005, Feb. 2002.
BibTeX
[26]梅谷 真也, 井上 美智子, 増澤 利光, 藤原 秀雄,
"非同期共有メモリシステムにおけるポイント競合度適応型繰り返し改名アルゴリズム ,"
No. 2002006, Mar. 2002.
BibTeX
Abstract
[27]大谷 浩平, 大竹 哲史, 藤原 秀雄,
"縮退故障のテスト生成アルゴリズムを用いたパス遅延故障に対するテスト生成法 ,"
No. 2002007, Mar. 2002.
BibTeX
[28]永井 慎太郎, 大竹 哲史, 藤原 秀雄,
"レジスタ転送レベルでのデータフロー依存型回路の階層テスト容易化設計法 ,"
No. 2002008, Apr. 2002.
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Abstract
[29]Erik Larsson and Hideo Fujiwara,
"Optimal test time for system-on-chip designs using preemptive scheduling and reconfigurable wrappers,"
No. 2002011, July 2002.
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Abstract
[30]Tomokazu Yoneda and Hideo Fujiwara,
"Design for consecutive transparency of RTL circuits,"
No. 2002013, July 2002.
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[31]Tomokazu Yoneda, Tetsuo Uchiyama and Hideo Fujiwara,
"Area and time co-optimization for system-on-a-chip based on consecutive testability,"
No. 2003002, Feb. 2003.
BibTeX
[32]Michiko Inoue, Kazuhiro Suzuki, Hiroyuki Okamoto and Hideo Fujiwara,
"Test synthesis for strongly testable datapaths using datapath-controller functions,"
No. 2003005, May 2003.
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[33]Virendra Singh, Michiko Inoue, Kewal K. Saluja and Hideo Fujiwara,
"Software-based delay fault testing of processor cores,"
No. 2003006, June 2003.
BibTeX
[34]Tsuyoshi Iwagaki, Satoshi Ohtake and Hideo Fujiwara,
"Reducibility of sequential test generation to combinational test generation for several delay fault models,"
No. 2003009, Sep. 2003.
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[35]Tsuyoshi Iwagaki, Satoshi Ohtake and Hideo Fujiwara,
"A design scheme for delay fault testability of controllers using state transition information,"
No. 2003010, Sep. 2003.
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[36]Chia Yee Ooi and Hideo Fujiwara,
"Classification of sequential circuits based on combinational test generation complexity,"
No. 2004001, Jan. 2004.
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[37]Chia Yee Ooi and Hideo Fujiwara,
"Some tau-equivalent classes of sequential circuits,"
No. 2004002, June 2004.
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Abstract
[38]Virendra Singh, Michiko Inoue, Kewal K. Saluja and Hideo Fujiwara,
"Software-based delay fault self-testing of pipelined processor cores,"
No. 200406, Sep. 2004.
BibTeX
[39]Tsuyoshi Iwagaki, Satoshi Ohtake and Hideo Fujiwara,
"Acceleration of transition test generation for acyclic sequential circuits utilizing constrained combinational stuck-at test generation ,"
No. 2004009, Dec. 2004.
BibTeX
[40]吉川 祐樹, 大竹 哲史, 井上 美智子, 藤原 秀雄,
"単一端子変化遅延テストに基づくデータパスのテスト容易化設計 ,"
No. 2005001, Jan. 2005.
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[41]Chia Yee Ooi, Thomas Clouqueur and Hideo Fujiwara,
"Test generation complexity for stuck-at and path delay faults based on tau^k-notation,"
No. 2005003, May 2005.
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[42]Tomokazu Yoneda, Kimihiko Masuda and Hideo Fujiwara,
"Power-constrained test scheduling for multi-clock domain socs,"
No. 2005004, June 2005.
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[43]Yuki Yoshikawa, Satoshi Ohtake, Michiko Inoue and Hideo Fujiwara,
"Design for testability based on single-port-change delay testing for data paths,"
No. 2005005, Aug. 2005.
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[44]Yuki Yoshikawa, Satoshi Ohtake and Hideo Fujiwara,
"An approach to reduce over-testing of path delay faults in data paths using RT-level information,"
No. 2006001, Feb. 2006.
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[45]Chia Yee Ooi and Hideo Fujiwara,
"A new class of sequential circuits with acyclic test generation complexity,"
No. 2006003, May 2006.
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[46]Tomokazu Yoneda, Masahiro Imanishi and Hideo Fujiwara,
"An soc test scheduling algorithm using reconfigurable union wrappers,"
No. 2006006, Sep. 2006.
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[47]Tsuyoshi Suzuki, Michiko Inoue and Hideo Fujiwara,
"Efficient mutual exclusion algorithm for high system congestion,"
No. 2009001, Jan. 2009.
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