Assistant Professor
Satoshi Ohtake
Address
Department of Information Processing, Graduate School of Information Science, Nara Institute of Science and Technology
Kansai Science City, Nara 630-0192, Japan
Phone: +81-743-72-5222
Fax: +81-743-72-5229
E-mail: ohtake (at) is.naist.jp
Education
Experience
Research Interests
  1. Logic Design and Test / Design Automation for Computers
    2. VLSI CAD, High-Level Synthesis for Testability, Logic Synthesis for Testability, Design for Testability, Test Synthesis, Test Generation, Fault Simulation, etc.
  2. Highly Reliable Design / Fault Tolerant Design of Computers
    3. Built In Self Test for VLSIs, Asynchronous Sequential Circuit Design, etc.
  3. Hardware/Software Co-Design
    4. CAD for H/S Co-Design, etc.
Publications
I. TECHNICAL PAPERS
  1. H. Fujiwara, S. Ohtake, and T. Takasaki, "Sequential circuit structure with combinational test generation complexity and its application," IEICE Trans. (DI), Vol.J80-D-I, No.2, pp.155-163, Feb. 1997. (In Japanese)
  2. S. Ohtake, T. Inoue, and H. Fujiwara, "An approach to sequential test generation by circuit pseudo-transformation," Trans. of IPSJ, Vol.38, No.5, pp.1040-1049, May 1997. (In Japanese)
  3. S. Ohtake, T. Masuzawa, and H. Fujiwara, "A non-scan DFT method for controllers to provide complete fault efficiency," IEICE Trans. (DI), Vol.J81-D-I, No.12, pp.59-1270, Dec. 1998. (In Japanese)
  4. S. Ohtake, T. Masuzawa and H. Fujiwara, "A non-scan approach to DFT for controllers achieving 100% fault efficiency," Journal of Electronic Testing: Theory and Applications (JETTA), Vol.16, No.5, pp.553-566, Oct. 2000.
  5. S. Nagai, H. Wada, S. Ohtake and H. Fujiwara, "A non-scan DFT method for RTL circuits based on fixed-control testability," IEICE Trans. (DI), Vol.J84-D-I, No.5, pp.454-465, May 2001. (In Japanese)
  6. Md. Altaf-Ul-Amin, S. Ohtake and H. Fujiwara, "Design for hierarchical two-pattern testability of data paths," IEICE Trans. on Information and Systems, Vol.E85-D, No.6, pp.975-984, Jun. 2002.
  7. S. Nagai, S. Ohtake and H. Fujiwara, "A method of design for hierarchical testability for data flow intensive circuits at register-transfer level," Journal of IPSJ, Vol. 43, No. 5, pp.1278-1289, May 2002. (In Japanese)
  8. Md. Altaf-Ul-Amin, S. Ohtake and H. Fujiwara, "Design for two-pattern testability of controller-data path circuits," IEICE Trans. on Information and Systems, Vol.E86-D, No.6, pp.1042-1049, June 2003.
  9. S. Ohtake, H. Wada, T. Masuzawa and H. Fujiwara, "A non-scan DFT method at register-transfer level to achieve 100% fault efficiency," Journal of IPSJ, Vol.44, No.5, pp.1266-1275, May 2003..
  10. S. Miwa, S. Ohtake and H. Fujiwara, "A new class of sequential circuits with combinational test generation complexity for path delay faults," IEICE Trans. (DI), Vol. J86-D-I, No. 11, pp.809-820, Nov. 2003. (In Japanese)
  11. T. Iwagaki, S. Ohtake and H. Fujiwara, "A test generation method for path delay faults in sequential circuits with discontinuous reconvergence structure," Trans. of IEICE (DI), Vol. J86-D-I, No. 12, pp.872-883, Dec. 2003. (In Japanese)
  12. D. K. Das, S. Ohtake and H. Fujiwara, "New DFT techniques of non-scan sequential circuits with complete fault efficiency," Journal of Electronic Testing:  Theory and Applications (JETTA), Vol. 20, No. 3, pp.315-323, June 2004..
  13. T. Iwagaki, S. Ohtake and H. Fujiwara, "A design scheme for delay testing of controllers using state transition information," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences (Special Section on VLSI Design and CAD Algorithms), Vol.E87-A, No.12, pp.3200-3207, Dec. 2004.
  14. K. Ohtani , S. Ohtake and H. Fujiwara, "A test generation method for path delay faults using stuck-at fault test generation algorithms," IEICE Trans. (DI), Vol.J88-D-I, No.6, pp.1057-1064, June 2005. (In Japanese)
  15. Y. Yoshikawa, S. Ohtake, M. Inoue and H. Fujiwara, "Non-scan design for single-port-change delay fault testability," Journal of IPSJ, Vol. 47, No. 6, pp.1619-1628, June 2006.
  16. H. Iwata, T. Yoneda, S. Ohtake and H. Fujiwara, " A DFT method based on partially strong testability of RTL data paths to guarantee complete fault efficiency," IEICE Trans. (DI), Vol. 89-D, No. 8, pp.1643-1653, Aug. 2006. (In Japanese)
  17. M. Nakazato, S. Ohtake, K. K. Saluja and H. Fujiwara, "Acceleration of test generation for sequential circuits using knowledge obtained from synthesis for testability," IEICE Transactions on Information and Systems, Vol. E90-D, No. 1, pp.296-305, Jan. 2007.
  18. M. Nakazato, M. Inoue, S. Ohtake and　H. Fujiwara, "Design for testability method to avoid error masking of software-based self-test for processors," IEICE Transasction on Information and Systems. (To appear)
II. INTERNATIONAL CONFERENCES
  1. S. Ohtake, T. Inoue, and H. Fujiwara, "Sequential test generation based on circuit pseudo-transformation," the 6th IEEE Asian Test Symposium (ATS'97), pp.62-67, Nov. 1997.
  2. S. Ohtake, T. Masuzawa, and H. Fujiwara, "A non-scan DFT method for controllers to achieve complete fault efficiency," the 7th IEEE Asian Test Symposium (ATS'98), pp.204-211, Dec. 1998.
  3. D. K. Das, S. Ohtake, and H. Fujiwara, "New DFT techniques of non-scan sequential circuits with complete fault efficiency," the 8th IEEE Asian Test Symposium (ATS'99), pp.263-268, Nov. 1999.
  4. S. Ohtake, M. Inoue, and H. Fujiwara, "A method of test generation for weakly testable data paths using test knowledge extracted from RTL description," the 8th IEEE Asian Test Symposium (ATS'99), pp.5-12, Nov. 1999.
  5. S. Ohtake, H. Wada, T. Masuzawa and H. Fujiwara, "A Non-Scan DFT Method at Register-Transfer Level to Achieve Complete Fault Efficiency," Asia and South Pacific Design Automation Conference 2000, pp.599-604, Jan. 2000.
  6. S. Ohtake, S. Nagai, H. Wada and H. Fujiwara, "A DFT method at RTL based on fixed-control testability to achieve 100% fault efficiency," IEEE Workshop on RTL ATPG & DFT 2000, Sep. 2000.
  7. S. Ohtake, S. Nagai, H. Wada and H. Fujiwara, "A DFT method for RTL circuits to achieve complete fault efficiency based on fixed-control testability," Asia and South Pacific Design Automation Conference 2001, pp.331-334, Jan. 2001.
  8. D. K. Das, B. B. Bhattacharya, S. Ohtake and H. Fujiwara, "Testable design of sequential circuits with improved fault efficiency," VLSI Design 2001, pp.128-133, Jan. 2001.
  9. Md. Altaf-Ul-Amin, S. Ohtake and H. Fujiwara, "Design for hierarchical two-pattern testability of data paths," the 10th IEEE Asian Test Symposium, pp.11-16, Nov. 2001.
  10. S. Nagai, S. Ohtake and H. Fujiwara, "A design for hierarchical testability for RTL data paths using extended data flow graphs," IEEE Workshop on RTL ATPG and Test, pp.128-133, Nov. 2001.
  11. S. Ohtake, S. Miwa and H. Fujiwara, "A method of test generation for path delay faults in balanced sequential circuits," VLSI Test Symposium 2002, pp.321-327, May. 2002.
  12. Md. Altaf-Ul-Amin, S. Ohtake and H. Fujiwara, "Design for two-pattern testability of controller-data path circuits," the 11th IEEE Asian Test Symposium, pp.73-79, 2002.
  13. S. Ohtake, K. Ohtani and H. Fujiwara, "A method of test generation for path delay faults using stuck-at fault test generation algorithms," Design Automation and Test in Europe 2003 (DATE03), pp.310-315, Mar. 2003.
  14. T. Iwagaki, S. Ohtake and H. Fujiwara, "A path delay test generation method for sequential circuits based on reducibility to combinational test generation," IEEE European Test Workshop 2003 (ETW'03), May 2003.
  15. T. Iwagaki, S. Ohtake and H. Fujiwara, "Reducibility of sequential test generation to combinational test generation for several delay fault models," the 12th IEEE Asian Test Symposium (ATS'03), pp.58-63, Nov. 2003.
  16. T. Iwagaki, S. Ohtake and H. Fujiwara, "An approach to design for delay fault testability of controllers," IEEE Workshop on RTL and High Level Testing  (WRTLT'03), pp.79-85, Nov. 2003.
  17. T. Iwagaki, S. Ohtake and H. Fujiwara, "A design scheme for delay fault testability of controllers using state transition information," European Test Symposium 2004 (ETS'04), pp.168-173, May 2004.
  18. M. Comte, S. Ohtake, H. Fujiwara and M. Renovell, "Electrical behavior of GOS faults in domino logic,"  The 8th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS), April 2005, pp.210-215, Apr. 2005.
  19. T. Iwagaki, S. Ohtake and H. Fujiwara, "Acceleration of transition test generation for acyclic sequential circuits utilizing constrained combinational stuck-at test generation," European Test Symposium 2005 (ETS'05), May 2995, pp.48-53, May 2005.
  20. M. Comte, S. Ohtake, H. Fujiwara and M. Renovell, "Electrical Analysis of a domino logic cell with GOS faults," IEEE International Workshop on Current & Defect Based Testing 2005, May 2005.
  21. M. Nakazato, S. Ohtake and H. Fujiwara, "Acceleration of test generation for sequential circuits using knowledge obtained from synthesis for testability," the 6th IEEE Workshop on RTL and High Level Testing (WRTLT'05), pp.50-60, 2005.
  22. H. Iwata, T. Yoneda, S. Ohtake and H. Fujiwara,  "A DFT method for RTL data paths based on partially strong testability to guarantee complete fault efficiency," the 14th IEEE Asian Test Symposium (ATS'05), pp.306-311, Dec. 2005.
  23. Y. Yoshikawa, S. Ohtake, M. Inoue and H. Fujiwara, "Design for testability based on single-port-change delay testing for data paths," the 14th IEEE Asian Test Symposium (ATS'05),  pp.254-259, Dec. 2005.
  24. M. Renovell, M. Comte, S. Ohtake and H. Fujiwara, "Electrical behavior of GOS fault affected domino logic cell," Third IEEE International Workshop on Electronic Design, Test & Applications (DELTA 2006), 17-19 Jan. 2006.
  25. I. Polian, B. Becker, M. Nakazato, S. Ohtake and H. Fujiwara, "Period of grace: a new paradigm for efficient soft error hardening," 18. ITG/GI/GMM Workshop Testmethoden und Zuverlassigkeit von Schaltungen und Systemen, pp.41-45, Mar. 2006.
  26. Y. Yoshikawa, S. Ohtake and H. Fujiwara, "An approach to reduce over-testing of path delay faults in data paths using RT-level information," Digest of Papers, the11th IEEE European Test Symposium (ETS'06), pp.146-151, May 2006.
  27. T. Iwagaki, S. Ohtake and H. Fujiwara, "A new test generation model for broadside transition testing of partial scan circuits," IFIP International Conference on Very Large Scale Integration (VLSI-SoC 2006), pp.308-313, Oct. 16-18, 2006.
  28. I. Polian, B. Becker, M. Nakazato, S. Ohtake and H. Fujiwara, "Low-cost hardening of image processing applications against soft errors,"  the 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'06), pp.274-279, Oct. 2006.
  29. M. Nakazato, S. Ohtake, M. Inoue and H. Fujiwara, "Design for testability of software-based self-test for processors," the 15th IEEE Asian Test Symposium (ATS'06), pp.375-380, Nov. 2006.
  30. S. Ohtake, K. Yabuki and H. Fujiwara, "Delay testing for application-specific interconnects of FPGAs based on inphase structure," Digest of Papers, the 12th IEEE European Test Symposium (ETS'07), pp.131-136, May. 2006.
  31. Y. Yoshikawa, S. Ohtake and H. Fujiwara, "False path identification using RTL information and its application to over-testing reduction for delay faults," the 16th IEEE Asian Test Symposium (ATS'07), Oct. 2007.
  32. T. Iwagaki, S. Ohtake, M. Kaneko and H. Fujiwara, "Efficient path delay test generation based on stuck-at test generation using checker circuitry," the 25th IEEE/ACM International Conference on Computer-Aided Design (ICCAD'07), Nov. 2007.
  33. Y. Yoshikawa, S. Ohtake and H. Fujiwara, "RTL don’t care path identification and synthesis for transforming don’t care paths into false paths," the 8th IEEE Workshop on RTL and High Level Testing (WRTLT'07), Oct. 2007.
  34. T. Iwagaki and S. Ohtake, "Generation of power-constrained scan tests and its difficulty," the 2nd IEEE International Design and Test Workshop (IDT'07), Dec. 2007.
III. TECHNICAL REPORTS
  1. S. Ohtake, T. Inoue, and H. Fujiwara, "An approach to sequential test generation by circuit pseudo-transformation," Technical Report of IEICE, (FTS96-42), Vol.96, No.291, Oct. 1996. (In Japanese)
  2. S. Ohtake, T. Masuzawa, and H. Fujiwara, "A non-scan DFT method for controllers to provide complete fault efficiency," Technical Report of IEICE, (FTS97-63), Vol.97, No.419, Dec. 1997. (In Japanese)
  3. D. K. Das, S. Ohtake, and H. Fujiwara, "New DFT techniques of non-scan sequential circuits with complete fault efficiency," Technical Report of IEICE, (FTS98-115), Vol.98, No.488, pp.73-80, Dec. 1998.
  4. S. Ohtake, H. Wada, T. Masuzawa, and H. Fujiwara, "A Non-scan DFT method at register-transfer level to achieve complete fault efficiency," Technical Report of IEICE, (VLD99-81, ICD99-210, FTS99-59), Vol.99, No.479, pp.47-54, Nov. 1999.
  5. S. Nagai, H. Wada, S. Ohtake, and H. Fujiwara, "A non-scan DFT method for RTL circuits based on fixed-control testability," Technical Report of IEICE, (VLD99-101), Vol.99, No.530, pp.29-36, Jan. 2000. (In Japanese)
  6. M. Amin, S. Ohtake, and H. Fujiwara, "Analyzing path delay fault testability of RTL data paths: A non-scan approach," Technical Report of IEICE, (FTS2000-71, VLD2000-106, ICD2000-163), Vol.100, No.473, pp.221-226, Nov. 2000.
  7. S. Miwa, S. Ohtake, and H. Fujiwara, "A new class of sequential circuits with combinational test generation complexity for path delay faults," Technical Report of IEICE FTS2000, Vol.100, No.620, pp.9-16, Feb. 2001. (In Japanese)
  8. S. Nagai, S. Ohtake and H. Fujiwara, "A Design for hierarchical testability for RTL data paths using extended data flow graph," Technical Report of IEICE FTS2001, Vol. 101, No. 467, pp.103-108, Nov. 2001. (In Japanese)
  9. T. Iwagaki, S. Ohtake and H. Fujiwara, "A method of partially enhanced scan design for path delay faults based on discontinuous reconvergence structure," Technical Report of IEICE (FTS2001), Vol.101, No.658, pp.53-60, Feb. 2002. (In Japanese)
  10. Md. Altaf-Ul-Amin, S. Ohtake and H. Fujiwara, "Design for two-pattern testability of controller-data path circuits," Technical Report of IEICE (FTS2001), Vol.101, No.658, pp.61-67, Feb. 2002.
  11. K. Ohtani, S. Ohtake and H. Fujiwara, "A method of test generation for path delay faults using stuck-at fault test generation algorithms," Technical Report of IEICE (FTS2001), Vol.101, No.658, pp.69-75, Feb. 2002. (In Japanese)
  12. S. Ohtake, M. Inoue and H. Fujiwara, "High level design for testability," Proceedings of the 2002 IEICE General Conference, Vol.SD-2-11, Mar. 2002. (In Japanese)
  13. M. Inoue, S. Ohtake and H. Fujiwara, "Partial scan designs equivalent to full scan designs," Proceedings of the 2002 IEICE General Conference, Vol.SD-2-10, Mar. 2002. (In Japanese)
  14. S. Nagai, S. Ohtake and H. Fujiwara, "A DFT method for RTL data paths based on strong testability to reduce test application time," Technical Report of IEICE (DC2002), Vol.102, No.658, pp.31-36, Feb. 2003. (In Japanese)
  15. T. Iwagaki, S. Ohtake and H. Fujiwara, "A method of design for delay fault testability of controllers," Technical Report of IEICE (DC2003), Vol.103, No.476, pp.25-30, Nov. 2003.
  16. Y. Murata, S. Ohtake and H. Fujiwara, "A method of DFT for data paths using bit-match function," Technical Report of IEICE (DC2004-58), Vol.104, No.478, pp.67-72, Dec. 2004. (In Japanese)
  17. Y. Yoshikawa, S. Ohtake, M. Inoue and H. Fujiwara, "Design for testability based on single-port-change delay fault testing for data paths," Technical Report of IEICE (DC2004-58), Vol.104, No.478, pp.73-78, Dec. 2004. (In Japanese)
  18. T. Iwagaki, S. Ohtake and H. Fujiwara, "Equivalence of sequential transition test generation and constrained combinational stuck-at test generation," Technical Report of IEICE (DC2004-96), Vol.104, No.664, pp.27-32, Feb. 2005.
  19. M. Nakazato, S. Ohtake and  H. Fujiwara, "Acceleration of test generation for sequential circuit using knowledge obtained from synthesis for testability," Technical Report of IEICE (DC2004-97), Vol.104, No.664, pp.33-38, Feb. 2005. (In Japanese)
  20. H. Iwata, T. Yoneda, S. Ohtake and H. Fujiwara, "Design for partially strong testability of data paths to guarantee complete fault efficiency," Technical Report of IEICE (DC2004-92), Vol.104, No.664, pp.1-6, Feb. 2005. (In Japanese)
  21. T. Iwagaki, S. Ohtake and H. Fujiwara, "A broadside test generation method for transition faults in partial scan circuits," Technical Report of IEICE (DC2005-54), Vol. 105, No. 443, pp.7-12, Dec. 2005. (In Japanese)
  22. K. Yabuki, S. Ohtake and H. Fujiwara, "Delay testing for application-specific interconnects of FPGAs based on inphase structure,"  Technical Report of IEICE (DC2005-??), Vol. 105, No. 442, pp.1-6, Dec. 2005. (In Japanese)
  23. N. Yamagata, M. Nakazato, K. Kambe, T. Yoneda, S. Ohtake, M. Inoue and H. Fujiwara, "DFT of instruction-based self-test for non-pipelined," Technical Report of IEICE (DC2005-73), Vol. 105, No. 607, pp.7-12, Feb. 2006. (In Japanese)
  24. M. Nakazato, S. Ohtake, M. Inoue and H. Fujiwara, " Design for testability of software-based self-test for processors," Vol. 106, No. 92, pp.49-54, June 2006. (In Japanese)
  25. T. Iwagaki, S. Ohtake, M. Kaneko and H. Fujiwara, "A test generation framework using checker circuits and its application to path delay test generation," Technical Report of IEICE (CAS2006-76), Vol. 106, No. 512, pp.37-42, Jan. 2007.
  26. Y. Yoshikawa, S. Ohtake and H. Fujiwara, "Reduction in over-testing of delay faults through false paths identification using RTL information," Technical Report of IEICE (DC2006-87), Vol. 106, No. 528, pp.43-48, Feb. 2007.
Awards
NAIST IS 1999 Best Student Award, March 2000.
IEICE ISS 2001 Year Paper Award, September 2002.
IEEE Workshop on RTL and High Level Testing  (WRTLT) 2003 Best Paper Award, November 2004.
IEEE International Workshop on Electronic Design, Test & Applications (DELTA) 2006 Best Paper Award, January 2006.
IEEE Workshop on RTL and High Level Testing  (WRTLT) 2005 Best Paper Award, November 2006.
Professional Activities
Local Arrangements Chair, 5th IEEE Workshop on RTL and High Level Testing (2004).
Registration Chair,15th IEEE Asian Test Symposium (2006).
Technical Program Committee Member, 12th Asia and South Pacific Design Automation Conference (2007).
Program Committee Member, 16th IEEE Asian Test Symposium (2007).
Program Committee Member, 8th IEEE Workshop on RTL and High Level Testing (2007).
Technical Program Committee Member, 13th Asia and South Pacific Design Automation Conference (2008).
Secretary, 17th IEEE Asian Test Symposium (2008).
Finance Chair, 9th IEEE Workshop on RTL and High Level Testing (2008).
Guest Associate Editor, Special Issue on Test and Verification of VLSI, IEICE Trans. on Information and Systems, IEICE Japan, Mar. 2007 - Mar. 2008
Member, IEEE Computer Society.
Member, IEICE.
Member, IPSJ.
Copyright 2001-2007, Satoshi Ohtake. All right reserved.